Patents by Inventor Carsten Hartig

Carsten Hartig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115621
    Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peter Moll, Martin Schmidt, Carsten Hartig, Matthias Ruhm, Stefan Thierbach, Stefan Rongen, Daniel Fischer, Andreas Schuring, Guido Überreiter
  • Publication number: 20170330782
    Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Peter MOLL, Martin SCHMIDT, Carsten HARTIG, Matthias RUHM, Stefan THIERBACH, Stefan RONGEN, Daniel FISCHER, Andreas SCHURING, Guido ÜBERREITER
  • Patent number: 9177873
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Alok Vaid, Carsten Hartig, Lokesh Subramany
  • Patent number: 9171765
    Abstract: Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Fischer, Carsten Hartig
  • Publication number: 20150243568
    Abstract: Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 27, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Daniel FISCHER, Carsten HARTIG
  • Publication number: 20150221565
    Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.
    Type: Application
    Filed: April 15, 2015
    Publication date: August 6, 2015
    Inventors: Guo Xiang NING, Carsten HARTIG, Paul ACKMANN, Fanghong GN
  • Patent number: 9091667
    Abstract: A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Adam Michal Urbanowicz, Carsten Hartig, Daniel Fischer
  • Patent number: 9029855
    Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 12, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guo Xiang Ning, Carsten Hartig, Paul Ackmann, Fanghong Gn
  • Publication number: 20150115153
    Abstract: A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Adam Michal Urbanowicz, Carsten Hartig, Daniel Fischer
  • Publication number: 20150033201
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Alok Vaid, Carsten Hartig, Lokesh Subramany
  • Patent number: 8892237
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Alok Vaid, Carsten Hartig
  • Publication number: 20140264334
    Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Globalfoundries Singapore Pte. Ltd.
    Inventors: Guo Xiang NING, Carsten Hartig, Paul Ackmann, Fanghong Gn
  • Publication number: 20140273299
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Alok Vaid, Carsten Hartig
  • Patent number: 7663766
    Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 16, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carsten Hartig, Jason P. Cain
  • Publication number: 20090059240
    Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 5, 2009
    Inventors: Carsten Hartig, Jason P. Cain
  • Patent number: 7410885
    Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 12, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Holger Schuehrer, Christin Bartsch, Carsten Hartig
  • Patent number: 7259091
    Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: August 21, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Holger Schuehrer, Carsten Hartig, Christin Bartsch, Kai Frohberg
  • Publication number: 20070026670
    Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.
    Type: Application
    Filed: May 17, 2006
    Publication date: February 1, 2007
    Inventors: Holger Schuehrer, Christin Bartsch, Carsten Hartig
  • Patent number: 7098140
    Abstract: Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: August 29, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthias Schaller, Christoph Schwan, Carsten Hartig
  • Publication number: 20060024951
    Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.
    Type: Application
    Filed: April 22, 2005
    Publication date: February 2, 2006
    Inventors: Holger Schuehrer, Carsten Hartig, Christin Bartsch, Kai Frohberg