Patents by Inventor Cathryn J. Christiansen

Cathryn J. Christiansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067056
    Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tian Shen, Anil Kumar, Yuncheng Song, Kong Boon Yeap, Ronald G. Filippi, JR., Linjun Cao, Seungman Choi, Cathryn J. Christiansen, Patrick R. Justison
  • Patent number: 10109599
    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
  • Publication number: 20180174982
    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 21, 2018
    Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
  • Publication number: 20180102318
    Abstract: A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current to flow from a first pad in a first row to a last pad in a last row via pads and resistive elements in each row. Fuses connecting pads in such an array can be included to allow tuning of resistance and/or other electrical properties.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 12, 2018
    Inventors: Cathryn J. Christiansen, Hanyi Ding, Baozhen Li
  • Patent number: 9851397
    Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Fen Chen, Cathryn J. Christiansen, Deborah M. Massey, Prakash Periasamy, Michael A. Shinosky
  • Patent number: 9831194
    Abstract: Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tom C. Lee, Cathryn J. Christiansen, Ian A. McCallum-Cook, Anthony K. Stamper
  • Patent number: 9780031
    Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
  • Patent number: 9768065
    Abstract: Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ping-Chuan Wang, Erdem Kaltalioglu, Ronald G. Filippi, Cathryn J. Christiansen
  • Patent number: 9685370
    Abstract: Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 20, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jonathan D. Chapple-Sokol, Cathryn J. Christiansen, Jeffrey P. Gambino, Tom C. Lee, William J. Murphy, Anthony K. Stamper
  • Publication number: 20160258998
    Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 8, 2016
    Inventors: Fen Chen, Cathryn J. Christiansen, Deborah M. Massey, Prakash Periasamy, Michael A. Shinosky
  • Patent number: 9435852
    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 6, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Andrew T. Kim, Cathryn J. Christiansen, Ping-Chuan Wang
  • Publication number: 20160181151
    Abstract: Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Jonathan D. Chapple-Sokol, Cathryn J. Christiansen, Jeffrey P. Gambino, Tom C. Lee, William J. Murphy, Anthony K. Stamper
  • Publication number: 20160071790
    Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Fen CHEN, Cathryn J. CHRISTIANSEN, Roger A. DUFRESNE, Charles W. GRIFFIN
  • Patent number: 9214427
    Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
  • Publication number: 20150243601
    Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.
    Type: Application
    Filed: May 13, 2015
    Publication date: August 27, 2015
    Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
  • Publication number: 20150221567
    Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 6, 2015
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
  • Patent number: 9087841
    Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 9059052
    Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
  • Publication number: 20150115400
    Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
  • Publication number: 20140339558
    Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne