Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.

Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract: Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router. Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract: Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router. Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract: A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag.

Abstract: An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.

Abstract: For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Abstract: A device, method, and system are disclosed. In one embodiment, the device includes an emulator to facilitate direct communication between an advanced host controller interface (AHCI) software driver and NAND host controller interface (HCI) hardware.