Patents by Inventor Chan-Mi Lee

Chan-Mi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875932
    Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsng Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Chan-Mi Lee
  • Publication number: 20160118331
    Abstract: A semiconductor device includes a substrate including a cell array region having a first active region and a peripheral circuit region having a second active region, an insulating layer pattern on the substrate and including a hole corresponding with the first active region, a DC conductive pattern in the hole, connected to the first active region, and buried in the substrate, a bit line connected to the DC conductive pattern and including a first bit line conductive pattern contacting the DC conductive pattern and covering a top surface of the insulating layer pattern, and a gate insulating layer and a gate electrode structure on the second active region, the gate electrode structure including a gate conductive pattern and a first gate electrode conductive pattern, the first gate electrode conductive pattern including a same material as the first bit line conductive pattern.
    Type: Application
    Filed: April 24, 2015
    Publication date: April 28, 2016
    Inventors: Young-kuk KIM, Chan-mi LEE, Sang-kwan KIM, Young-wook PARK
  • Patent number: 8872059
    Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wuk Park, Geum-Jung Seong, Kye-Hyun Baek, Yong-Jin Kim, Chan-Mi Lee
  • Patent number: 8841643
    Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Shin-Jae Kang, Sug-Woo Jung, Dong-Hyun Im, Chan-Mi Lee
  • Patent number: 8193507
    Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: June 5, 2012
    Assignee: SNU R&DB Foundation
    Inventors: Jae Sung Lee, Chan Mi Lee, Sun Il Kwon, Mikiko Ito, Hyun Suk Yoon, Sang Keun Park, Seong Jong Hong, Dong Soo Lee
  • Publication number: 20120119181
    Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 17, 2012
    Inventors: Gyu-Hwan OH, Shin-Jae Kang, Sug-Woo Jung, Dong-Hyun Im, Chan-Mi Lee
  • Publication number: 20120055908
    Abstract: Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.
    Type: Application
    Filed: August 29, 2011
    Publication date: March 8, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wuk Park, Geum-Jung Seong, Kye-Hyun Baek, Yong-Jin Kim, Chan-Mi Lee
  • Patent number: 8067285
    Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Chan-Mi Lee, Sang-Sup Jeong
  • Publication number: 20110192980
    Abstract: The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.
    Type: Application
    Filed: June 2, 2010
    Publication date: August 11, 2011
    Applicant: SNU R&DB FOUNDATION
    Inventors: Jae Sung Lee, Chan Mi Lee, Sun Il Kwon, Mikiko Ito, Hyun Suk Yoon, Sang Keun Park, Seong Jong Hong, Dong Soo Lee
  • Publication number: 20110151633
    Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Inventors: Jong-Chul PARK, Chan-Mi Lee, Sang-Sup Jeong
  • Publication number: 20090174039
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 9, 2009
    Inventors: Chan-Mi Lee, Jong-Chul Park