Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.

Abstract: A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function, additional in-system programming pins are multiplexed with programmable input/output pins used in functional operations. When an enable signal is received at the dedicated pin, the multiplexed pins relinquish their roles as programmable input/output pin to become in-system programming pins. A state machine controls the programming steps. The in-system programming structure can be cascaded in a "daisy chain" fashion.

Abstract: A sense amplifier circuit is disclosed which utilizes a field effect transistor having a negative threshold voltage to provide a faster switching speed for a given current consumption. A depletion mode transistor is utilized as the feedback transistor, with the gate of the depletion mode transistor being coupled to the output of the second stage of the sense amplifier. The first stage of the sense amplifier includes in addition to the depletion mode transistor a second field effect transistor connected in series with said feedback transistor, with the gate and drain of the second transistor being commonly connected. The sense amplifier circuit also includes third and fourth stages providing inversion and amplification of the signal provided at the output of the second stage, with the third and fourth stages comprising a depletion load inverter and a CMOS inverter, respectively.

Abstract: A programmable logic device is disclosed which includes sense amplifiers for determining the programmed/unprogrammed state of product terms coupled to respective ones of the sense amplifiers. A control circuit is provided for the sense amplifiers to permit, under control from a control signal, disabling sense amplifiers which are not being used in the achievement of the logical function of the programmable logic device to avoid unnecessary use of current by the sense amplifiers which are not operative for the function being implemented. In addition to eliminating current drain by the unused sense amplifier, the control circuit also ensures that a low output signal will always be provided at the output of the disabled sense amplifier to avoid potentially indicating an incorrect logical output from the sense amplifier which is connected to other devices in the programmable logic device.