Abstract: Systems and methods that encode and decode data in a manner that limits error propagation by parsing a data word of length n into a predetermined number of data blocks, individually encoding each data block into a single associated code block, and then combining each of the code blocks to form a resulting code word of length (n+1), resulting in a code rate of n/(n+1). By parsing and encoding the data word in this manner, errors that occur with respect to one or more bits of one code block will not be propagated throughout an entire data word during the decoding process.

Abstract: Systems and methods that encode and decode data in a manner that limits error propagation by parsing a data word of length n into a predetermined number of data blocks, individually encoding each data block into a single associated code block, and then combining each of the code blocks to form a resulting code word of length (n+1), resulting in a code rate of n/(n+1). By parsing and encoding the data word in this manner, errors that occur with respect to one or more bits of one code block will not be propagated throughout an entire data word during the decoding process.

Abstract: A track address pattern embedded in the servo zones of a storage medium for representing a track address identification having a binary bit length "n". The track addresses pattern embedded in the medium is recoded from a Gray-code representation of the track address identification and has a code rate of n/(n+1), where n.gtoreq.2. The recoded track address pattern (or codeword) is modeled from a Gray-code representation wherein a plurality of bit cells corresponding to a track address of the data storage apparatus are recoded to include a parity bit selected to maintain a selected parity for the track address pattern. More particularly, when a "1" occurs in the same bit cell location in two adjacent track address patterns, then the parity on "1"s up until the same bit cell location is the same for both of the m.sup.th and the (m-1).sup.th track address patterns and for the m.sup.th and the (m+1).sup.th track address patterns. Furthermore, the codewords provide that the bit cells of an m.sup.