Patents by Inventor Chandrasekara Kothandaraman
Chandrasekara Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411175Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.Type: GrantFiled: May 5, 2020Date of Patent: August 9, 2022Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Chandrasekara Kothandaraman, Nathan P. Marchack, Eugene J. O'Sullivan
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Patent number: 11216595Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: GrantFiled: September 21, 2019Date of Patent: January 4, 2022Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 10997321Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: GrantFiled: September 21, 2019Date of Patent: May 4, 2021Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 10804458Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a free magnetic layer formed on the tunnel barrier layer. A first boron-segregating layer is formed directly on the free magnetic layer. An anneal is performed to cause boron to leave the free magnetic layer at an interface with the first boron-segregating layer. A top electrode is formed over the memory stack.Type: GrantFiled: January 8, 2019Date of Patent: October 13, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS, CO., LTD.Inventors: Guohan Hu, Younghyun Kim, Chandrasekara Kothandaraman, Jeong-Heon Park
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Patent number: 10778422Abstract: Methods and systems for generating an identifier includes testing an operational characteristic for each device in an array of pairs of devices. Each pair of devices includes a first device and a second device. The first device of each pair has a higher inter-device uniformity for the operational characteristic than the second device of the pair. The operational characteristic between the first device and the second device is compared for each pair of devices to generate a respective identifier bit for each pair of devices. An identifier is generated from the identifier bits.Type: GrantFiled: July 13, 2016Date of Patent: September 15, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dirk Pfeiffer, Sami Rosenblatt, Chandrasekara Kothandaraman
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Publication number: 20200266342Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Applicant: International Business Machines CorporationInventors: Anthony J. ANNUNZIATA, Chandrasekara KOTHANDARAMAN, Nathan P. MARCHACK, Eugene J. O'SULLIVAN
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Patent number: 10721082Abstract: Methods and systems for generating an identifier include detecting emissions from a phosphor pattern with a sensor grid comprising one or more sensors when the phosphor pattern is stimulated with radiation. An output signal of each sensor in the sensor grid is compared to a threshold value to generate respective identifier bits. An identifier is generated from the identifier bits.Type: GrantFiled: July 18, 2016Date of Patent: July 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dirk Pfeiffer, Sami Rosenblatt, Chandrasekara Kothandaraman
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Patent number: 10566524Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.Type: GrantFiled: November 16, 2017Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
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Patent number: 10551254Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.Type: GrantFiled: March 21, 2018Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chandrasekara Kothandaraman, Sami Rosenblatt, Akil K. Sutton
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Publication number: 20200019731Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: ApplicationFiled: September 21, 2019Publication date: January 16, 2020Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Publication number: 20200019732Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: ApplicationFiled: September 21, 2019Publication date: January 16, 2020Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 10423805Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: GrantFiled: December 22, 2016Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Publication number: 20190140165Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a free magnetic layer formed on the tunnel barrier layer. A first boron-segregating layer is formed directly on the free magnetic layer. An anneal is performed to cause boron to leave the free magnetic layer at an interface with the first boron-segregating layer. A top electrode is formed over the memory stack.Type: ApplicationFiled: January 8, 2019Publication date: May 9, 2019Inventors: Guohan Hu, Younghyun Kim, Chandrasekara Kothandaraman, Jeong-Heon Park
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Patent number: 10230043Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a fixed magnetic layer, a tunnel barrier layer on the fixed magnetic layer, and a free magnetic layer formed on the tunnel barrier layer. A boron-segregating layer is formed directly on the free magnetic layer. The memory stack is etched into a pillar. A top electrode is formed over the pillar.Type: GrantFiled: March 21, 2017Date of Patent: March 12, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS, CO., LTD.Inventors: Guohan Hu, Younghyun Kim, Chandrasekara Kothandaraman, Jeong-Heon Park
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Publication number: 20180287054Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.Type: ApplicationFiled: November 16, 2017Publication date: October 4, 2018Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre
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Publication number: 20180277748Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a fixed magnetic layer, a tunnel barrier layer on the fixed magnetic layer, and a free magnetic layer formed on the tunnel barrier layer. A boron-segregating layer is formed directly on the free magnetic layer. The memory stack is etched into a pillar. A top electrode is formed over the pillar.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventors: Guohan Hu, Younghyun Kim, Chandrasekara Kothandaraman, Jeong-Heon Park
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Publication number: 20180217012Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.Type: ApplicationFiled: March 21, 2018Publication date: August 2, 2018Inventors: Chandrasekara Kothandaraman, Sami Rosenblatt, Akil K. Sutton
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Publication number: 20180181774Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 9970830Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.Type: GrantFiled: June 14, 2016Date of Patent: May 15, 2018Assignee: International Business Machines CorporationInventors: Chandrasekara Kothandaraman, Sami Rosenblatt, Akil K. Sutton
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Patent number: 9911914Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.Type: GrantFiled: March 28, 2017Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekara Kothandaraman, John R. Sporre