Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Abstract: According to exemplary embodiments, a rotor off-take assembly is provided by positioning an angled hole or aperture in a stator assembly. This angled hole provides improved pressure recovery and utilizes higher dynamic pressure to drive the bleed air flow into the off-take cavity.

Abstract: According to exemplary embodiments, a rotor off-take assembly is provided by positioning an angled hole or aperture in a stator assembly. This angled hole provides improved pressure recovery and utilizes higher dynamic pressure to drive the bleed air flow into the off-take cavity.

Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal.

Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.

Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide a count signal associated with external device latency. The count signal is captured responsive to the clock signal.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.

Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.