Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: A semiconductor device includes a semiconductor region, a first active region in the semiconductor region, a second active region in the semiconductor region, and a conductive gate disposed above the first active region and the second active region. A first contact of the conductive gate is configured to couple to a first node of a circuit associated with the semiconductor device. Moreover, a second contact of the conductive gate is configured to couple to a second node of a circuit associated with the semiconductor device. A resistive device is defined between the first contact and the second contact.

Abstract: A semiconductor device includes a semiconductor region, a first active region in the semiconductor region, a second active region in the semiconductor region, and a conductive gate disposed above the first active region and the second active region. A first contact of the conductive gate is configured to couple to a first node of a circuit associated with the semiconductor device. Moreover, a second contact of the conductive gate is configured to couple to a second node of a circuit associated with the semiconductor device. A resistive device is defined between the first contact and the second contact.

Abstract: I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) is disclosed. The ESD protection circuit has a RC module having a resistor and capacitor connected in series; and a current dissipation module for dissipating the ESD, wherein the capacitor is formed by a thick native gate oxide of a transistor, and wherein the thick native gate oxide prevents leakage current formed therethrough so that to avoid leakage current through the current dissipation module during a normal operation of the IC.

Abstract: I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) is disclosed. The ESD protection circuit has a RC module having a resistor and capacitor connected in series; and a current dissipation module for dissipating the ESD, wherein the capacitor is formed by a thick native gate oxide of a transistor, and wherein the thick native gate oxide prevents leakage current formed therethrough so that to avoid leakage current through the current dissipation module during a normal operation of the IC.

Abstract: A new method to reduce switching noise on an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a power supply, a ground, and a plurality of switchable capacitors. Each switchable capacitor is connected from the power supply to ground. The operating mode of the integrated circuit device is tracked. An optimal capacitance value is selected based on the operating mode. A set of switchable capacitors from the plurality of switchable capacitors is selected to thereby connect the optimal capacitance value from the power supply to ground.

Abstract: A new method to reduce switching noise on an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a power supply, a ground, and a plurality of switchable capacitors. Each switchable capacitor is connected from the power supply to ground. The operating mode of the integrated circuit device is tracked. An optimal capacitance value is selected based on the operating mode. A set of switchable capacitors from the plurality of switchable capacitors is selected to thereby connect the optimal capacitance value from the power supply to ground.

Abstract: A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.