Patents by Inventor Chang Heon Park

Chang Heon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9871045
    Abstract: A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 16, 2018
    Assignee: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung-Jin Yeom, Noh-Jung Kwak, Chang-Heon Park, Sun-Hwan Hwang
  • Patent number: 9728540
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 8, 2017
    Assignee: SK HYNIX INC.
    Inventors: Ky Hyun Han, Chang Heon Park, Dong Gu Choi
  • Publication number: 20160322364
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Application
    Filed: July 12, 2016
    Publication date: November 3, 2016
    Inventors: Ky Hyun HAN, Chang Heon PARK, Dong Gu CHOI
  • Patent number: 9419002
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventors: Ky Hyun Han, Chang Heon Park, Dong Gu Choi
  • Publication number: 20150235950
    Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.
    Type: Application
    Filed: August 29, 2014
    Publication date: August 20, 2015
    Inventors: Ky Hyun HAN, Chang Heon PARK, Dong Gu CHOI
  • Publication number: 20140353744
    Abstract: A semiconductor device includes a substrate including a first active region and second active regions, a bit line structure in contact the first active region, and storage node contacts in contact the second active regions. A top surface of the first active region is lower than the top surfaces of the second active regions.
    Type: Application
    Filed: October 18, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventors: Ho-Jin JUNG, Chang-Heon PARK, Dong-Goo CHOI, Joong-Gun YOO, Yeo-Jin YOON, Seong-Hwan AHN, Jin-Wook CHEONG
  • Patent number: 7608546
    Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: October 27, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Soo Park, Chang-Heon Park, Dong-Ryeol Lee
  • Publication number: 20090117748
    Abstract: A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas.
    Type: Application
    Filed: June 25, 2008
    Publication date: May 7, 2009
    Applicant: Hynix Semiconductor, Inc.
    Inventors: Dong Ryeol LEE, Chang Heon PARK, Hee Seung SHIN
  • Publication number: 20080182395
    Abstract: A method for fabricating a dual polysilicon gate includes providing a substrate, forming a gate oxide layer over the substrate, forming a polysilicon layer over the gate oxide layer, patterning the polysilicon layer in a condition of applying a relatively low first pressure or a relatively high first bias power, thereby forming gate patterns and exposing a given portion of the gate oxide layer, and forming an oxide layer over the exposed given portion of the gate oxide layer by using a plasma oxidation process while performing an over-etch process on the gate patterns in a condition of applying a second pressure higher than the first pressure or a second bias power lower than the first bias power.
    Type: Application
    Filed: December 30, 2007
    Publication date: July 31, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Chang-Heon PARK, Dong-Ryeol Lee
  • Publication number: 20080160653
    Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate that includes a cell region and a peripheral region. A first hard mask layer, a second hard mask layer, and an anti-reflective coating layer are formed over the etch target layer. A photosensitive pattern is formed over the anti-reflective coating layer. The anti-reflective coating layer is etched to have a width smaller than the width of the photosensitive pattern. The second hard mask layer is etched. A main etching and an over-etching are performed on the first hard mask layer. The etch target layer is then etched.
    Type: Application
    Filed: June 20, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Soo PARK, Chang-Heon Park, Dong-Ryeol Lee
  • Patent number: 6589861
    Abstract: A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: July 8, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Heon Park, Yun Seok Cho
  • Patent number: 6465321
    Abstract: There is disclosed a method of forming a storage node in a semiconductor device capable of forming a storage node in a vertical structure, by forming a hard mask used to form a noble storage node using a TiN film deposited in a spacer shape on an oxide film and over the oxide film.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 15, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyeon Sang Shin, Chang Heon Park, Myung Pil Kim
  • Publication number: 20020081835
    Abstract: A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 27, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventors: Chang Heon Park, Yun Seok Cho