Patents by Inventor Chang Hwi LEE

Chang Hwi LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935876
    Abstract: A light-emitting element ink, a display device, and a method of fabricating the display device are provided. The light-emitting element ink includes a light-emitting element solvent, light-emitting elements dispersed in the light-emitting element solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film that surrounds parts of outer surfaces of the semiconductor layers, and a surfactant dispersed in the light-emitting element solvent, the surfactant including a fluorine-based and/or a silicon-based surfactant.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Bo Sim, Duk Ki Kim, Yong Hwi Kim, Hyo Jin Ko, Chang Hee Lee, Chan Woo Joo, Jae Kook Ha, Na Mi Hong
  • Publication number: 20240003961
    Abstract: The test circuit monitoring positive bias temperature instability (PBTI) includes a PBTI monitoring unit driven according to a power voltage, the PBTI monitoring unit outputting an output voltage having a potential that is equal to or lower than a potential of the power voltage according to a PBTI degradation rate of an NMOS transistor; and a degradation determiner for determining the PBTI degradation rate by comparing the potential of the output voltage to the potential of the power voltage.
    Type: Application
    Filed: December 12, 2022
    Publication date: January 4, 2024
    Applicant: SK hynix Inc.
    Inventors: Min Cheol KIM, Mi Ran KIM, Chang Hwi LEE
  • Patent number: 11355926
    Abstract: A test device is disclosed. The test device includes an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power-supply line, a ground line, or a substrate line, a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design, and a discharge circuit configured to allow capacitance stored in the capacitor circuit to be discharged to the substrate line.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Woo Kim, Chang Hwi Lee, Man Ho Seung
  • Patent number: 11195827
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Jin Woo Kim, Hyun Duck Lee, Seung Yeop Lee, Ju Hyeong Lee
  • Patent number: 11158626
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Hee Jeong Son, Ki Ryong Jung, Seung Yeop Lee
  • Publication number: 20200273856
    Abstract: A semiconductor integrated circuit may include a first power line, a second power line, a third power line and a protection circuit. The first power line may receive an external voltage. The second power line may receive a voltage greater than the external voltage. The third power line may receive a voltage less than the external voltage applied to the first power line and the voltage applied to the second power line. The protection circuit may from a current path between the first power line, the second power line and the third power line when a surge voltage may be applied to the first power line to discharge the surge voltage to the third power line.
    Type: Application
    Filed: November 5, 2019
    Publication date: August 27, 2020
    Applicant: SK hynix Inc.
    Inventors: Chang Hwi LEE, Jung Eon MOON, Hyeng Ouk LEE, Joung Cheul CHOI
  • Publication number: 20200274352
    Abstract: A test device is disclosed. The test device includes an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power-supply line, a ground line, or a substrate line, a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design, and a discharge circuit configured to allow capacitance stored in the capacitor circuit to be discharged to the substrate line.
    Type: Application
    Filed: October 21, 2019
    Publication date: August 27, 2020
    Applicant: SK hynix Inc.
    Inventors: Jin Woo KIM, Chang Hwi LEE, Man Ho SEUNG
  • Publication number: 20190379204
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.
    Type: Application
    Filed: January 25, 2019
    Publication date: December 12, 2019
    Applicant: SK hynix Inc.
    Inventors: Chang Hwi LEE, Jin Woo KIM, Hyun Duck LEE, Seung Yeop LEE, Ju Hyeong LEE
  • Patent number: 10444265
    Abstract: A current level extraction method for preventing cutoff is disclosed. The method may include starting a voltage sweep to an interconnection structure at a certain temperature, measuring an initial resistance of the interconnection structure, calculating a measured resistance of the interconnection structure according to a corresponding input voltage, determining whether or not a resistance ratio of the measured resistance of the interconnection structure to the initial resistance is equal to or less than a preset value, updating a current value corresponding to measured resistance to a potential maximum current level and repeating the step of calculating the measured resistance when the resistance ratio of the interconnection structure is equal to or less than the preset value, and setting the current value corresponding to the measured resistance as a maximum current level when the resistance ratio of the interconnection structure is greater than the preset value.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Sung Bae Kim, Si Woo Lee, Man Ho Seung
  • Publication number: 20190018049
    Abstract: A current level extraction method for preventing cutoff is disclosed. The method may include starting a voltage sweep to an interconnection structure at a certain temperature, measuring an initial resistance of the interconnection structure, calculating a measured resistance of the interconnection structure according to a corresponding input voltage, determining whether or not a resistance ratio of the measured resistance of the interconnection structure to the initial resistance is equal to or less than a preset value, updating a current value corresponding to measured resistance to a potential maximum current level and repeating the step of calculating the measured resistance when the resistance ratio of the interconnection structure is equal to or less than the preset value, and setting the current value corresponding to the measured resistance as a maximum current level when the resistance ratio of the interconnection structure is greater than the preset value.
    Type: Application
    Filed: January 11, 2018
    Publication date: January 17, 2019
    Applicant: SK hynix Inc.
    Inventors: Chang Hwi LEE, Sung Bae KIM, Si Woo LEE, Man Ho SEUNG
  • Publication number: 20180350797
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Application
    Filed: January 19, 2018
    Publication date: December 6, 2018
    Inventors: Chang Hwi LEE, Hee Jeong SON, Ki Ryong JUNG, Seung Yeop LEE