Patents by Inventor Chang Hyuk Lee
Chang Hyuk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9966215Abstract: The disclosure relates to a permanent magnet actuator comprising: a stator iron core having a space therein-side, and having a first wall and a second wall opposing the first wall; a movable element moving reciprocally between the first wall and the second wall, along a moving axis which connects the first wall and the second wall inside the space; a first magnetomotive force supplying body and a second magnetomotive force supplying body disposed respectively on the first wall and the second wall, so as to supply a magnetomotive force to the movable element for the reciprocal movement thereof, wherein, at least one of the first magnetomotive force supplying body and the second magnetomotive force supplying body selectively produces a bidirectional magnetomotive force; a permanent magnet disposed between the first magnetomotive force supplying body and the second magnetomotive force supplying body, and providing a coercive force to the movable element for maintaining the state thereof; and a driving circuit coType: GrantFiled: May 24, 2013Date of Patent: May 8, 2018Assignee: Entec Electric and Electronic Co., Ltd.Inventors: Young Bong Bang, Chang Hyuk Lee, Ji Won Choi, Young Il Kim, Heung Ryeol Koh, Myeong Seob Choi
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Patent number: 9895087Abstract: A wearable apparatus for measuring position and action of an arm includes: a main frame worn on an upper body of a user; and an arm motion-measuring unit connected to a side of the main frame, having a plurality of joints, and worn on an arm of a user, in which at least any one of the joints of the arm motion-measuring unit has a straight-motional degree of freedom. Accordingly, an instructor can conveniently move both arms in the apparatus, can precisely instruct a two-arm robot in motions of the instructor's arms, can reduce learning time of the robot, and can make the robot quickly and accurately learn the motions.Type: GrantFiled: October 19, 2015Date of Patent: February 20, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hoo-Man Lee, Joong-Bae Kim, Young-Bong Bang, Chang-Hyuk Lee, Ji-Won Choi
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Publication number: 20170055883Abstract: A wearable apparatus for measuring position and action of an arm includes: a main frame worn on an upper body of a user; and an arm motion-measuring unit connected to a side of the main frame, having a plurality of joints, and worn on an arm of a user, in which at least any one of the joints of the arm motion-measuring unit has a straight-motional degree of freedom. Accordingly, an instructor can conveniently move both arms in the apparatus, can precisely instruct a two-arm robot in motions of the instructor's arms, can reduce learning time of the robot, and can make the robot quickly and accurately learn the motions.Type: ApplicationFiled: October 19, 2015Publication date: March 2, 2017Inventors: Hoo-Man LEE, Joong-Bae KIM, Young-Bong BANG, Chang-Hyuk LEE, Ji-Won CHOI
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Publication number: 20160086756Abstract: The disclosure relates to a permanent magnet actuator comprising: a stator iron core having a space therein-side, and having a first wall and a second wall opposing the first wall; a movable element moving reciprocally between the first wall and the second wall, along a moving axis which connects the first wall and the second wall inside the space; a first magnetomotive force supplying body and a second magnetomotive force supplying body disposed respectively on the first wall and the second wall, so as to supply a magnetomotive force to the movable element for the reciprocal movement thereof, wherein, at least one of the first magnetomotive force supplying body and the second magnetomotive force supplying body selectively produces a bidirectional magnetomotive force; a permanent magnet disposed between the first magnetomotive force supplying body and the second magnetomotive force supplying body, and providing a coercive force to the movable element for maintaining the state thereof; and a driving circuit coType: ApplicationFiled: May 24, 2013Publication date: March 24, 2016Inventors: Young Bong BANG, Chang Hyuk LEE, Ji Won CHOI, Young Il KIM, Heung Ryeol KOH, Myeong Seob CHOI
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Patent number: 9159435Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.Type: GrantFiled: August 31, 2012Date of Patent: October 13, 2015Assignee: SK Hynix Inc.Inventors: Chang Won Yang, Hwang Huh, Myung Jin Park, Chang Hyuk Lee
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Patent number: 9123396Abstract: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.Type: GrantFiled: August 6, 2013Date of Patent: September 1, 2015Assignee: SK HYNIX INC.Inventors: Chang Man Son, Chang Hyuk Lee, Go Hyun Lee, Kwang Ho Baek
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Publication number: 20140313809Abstract: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to couple local lines of the memory block to global lines. The first to third conductive patterns are arranged in different layers over the memory block.Type: ApplicationFiled: August 6, 2013Publication date: October 23, 2014Applicant: SK HYNIX INC.Inventors: Chang Man SON, Chang Hyuk LEE, Go Hyun LEE, Kwang Ho BAEK
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Publication number: 20130163343Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.Type: ApplicationFiled: August 31, 2012Publication date: June 27, 2013Inventors: Chang Won YANG, Hwang Huh, Myung jin Park, Chang Hyuk Lee
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Publication number: 20130093472Abstract: A semiconductor integrated circuit includes a driving unit, a first current path and a second current path. The driving unit applies a power supply voltage to a drive node in response to a control signal. The first current path couples the drive node and an output node. The second current path couples the drive node and the output node. The first current path and the second current path are coupled in parallel between the drive node and the output node.Type: ApplicationFiled: December 30, 2011Publication date: April 18, 2013Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hae Uk LEE, Chang Hyuk LEE, Jae Yong CHA, Ha Min SUNG, Yi Seul PARK
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Patent number: 7733736Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.Type: GrantFiled: May 20, 2008Date of Patent: June 8, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Hi-Hyun Han, Chang-Hyuk Lee, Ju-Young Seo
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Patent number: 7710797Abstract: A semiconductor memory device stably performs a write operation with reduced current consumption. The semiconductor memory device includes a global data, a control unit, a termination resistor unit, and a storage unit. The global data line transmits data. The control unit generates a global control signal during a read operation or a write operation. The termination resistance unit supplies termination resistance to the global data line in response to the global control signal. The storage unit stores the data transmitted to the global data line while the termination resistance unit is inactivated. A method for driving the semiconductor memory device includes detecting a read operation or a write operation and supplying termination resistance when the read or write operation is detected.Type: GrantFiled: June 29, 2007Date of Patent: May 4, 2010Assignee: Hynix Semiconductors, Inc.Inventor: Chang-Hyuk Lee
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Patent number: 7586797Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.Type: GrantFiled: April 30, 2008Date of Patent: September 8, 2009Assignee: Hynix Semiconductor Inc.Inventor: Chang Hyuk Lee
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Publication number: 20080279034Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.Type: ApplicationFiled: April 30, 2008Publication date: November 13, 2008Inventor: Chang Hyuk Lee
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Patent number: 7447090Abstract: A semiconductor memory device includes: a first bit line sense amplifier array for amplifying a data input to a first bit line pair coupled to cells; a second bit line sense amplifier array for amplifying a data input to a second bit line pair coupled to the cells; and a control unit for activating one of the first and second bit line sense amplifier arrays and, after a predetermined time, for activating the other bit line sense amplifier array in response to an active signal and a column address information signal.Type: GrantFiled: December 29, 2006Date of Patent: November 4, 2008Assignee: Hynix Semiconductor Inc.Inventor: Chang-Hyuk Lee
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Publication number: 20080225628Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.Type: ApplicationFiled: May 20, 2008Publication date: September 18, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Hi-Hyun Han, Chang-Hyuk Lee, Ju-Young Seo
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Patent number: 7388804Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.Type: GrantFiled: June 30, 2006Date of Patent: June 17, 2008Assignee: Hynix Semiconductor Inc.Inventors: Hi-Hyun Han, Chang-Hyuk Lee, Ju-Young Seo
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Patent number: 7385860Abstract: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.Type: GrantFiled: June 12, 2006Date of Patent: June 10, 2008Assignee: Hynix Semiconductor Inc.Inventor: Chang Hyuk Lee
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Patent number: 7369448Abstract: An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data processing speed by advancing an operation time point of a data bus writer is provided.Type: GrantFiled: January 18, 2007Date of Patent: May 6, 2008Assignee: Hynix Semiconductor Inc.Inventor: Chang Hyuk Lee
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Patent number: 7363555Abstract: A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on a test mode signal and a plurality of control clock signals; a logic operation unit for performing a logic operation to the data outputted to the plurality of global input/output lines and for outputting a result of the logic operation to a test global input/output line; and a switching unit coupled to the test global input/output line and the plurality of global input/output lines for selectively passing data of the test global input/output line and data of the global input/output lines based on the test mode signal and the plurality of control clock signals.Type: GrantFiled: December 21, 2004Date of Patent: April 22, 2008Assignee: Hynix Semiconductor, Inc.Inventor: Chang-Hyuk Lee
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Patent number: 7362629Abstract: A redundant circuit includes a plurality of bit line sense amp arrays including different local data buses, sharing one bit line sense amp, and being formed adjacently to each other, an input/output fuse unit for outputting a selection signal with different logic state depending on whether or not a first fuse is cut upon activation of a row active operation control signal, a fuse set for providing a redundant signal with different logic state based on whether or not a second fuse is cut and repair addresses upon activation of the row active operation control signal, and a redundant controller for logically operating the selection signal, the redundant signal and a strobe signal to thereby generate a bus control signal to selectively connect the bit line sense amp to the different local data buses.Type: GrantFiled: June 29, 2006Date of Patent: April 22, 2008Assignee: Hynix Semiconductor, Inc.Inventor: Chang-Hyuk Lee