Patents by Inventor Chang Kil KIM

Chang Kil KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965668
    Abstract: A device for managing a temperature according to an embodiment of the present disclosure includes a conversion controller that estimates an indoor set temperature based on a temperature of air returned from a target zone and an operating time of a state converter, and controls a state conversion amount of the state converter by comparing the estimated indoor set temperature with the temperature of the returned air, and a heat exchanger for varying the temperature of the returned air and providing the air whose temperature is varied to the target zone.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 23, 2024
    Assignee: Kyungdong Navien Co., Ltd.
    Inventors: Seung Kil Son, Chang Heoi Heo, Nam Soo Do, Jung Keom Kim
  • Patent number: 8946706
    Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chang Kil Kim
  • Publication number: 20130147509
    Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.
    Type: Application
    Filed: August 30, 2012
    Publication date: June 13, 2013
    Inventor: Chang Kil KIM