Abstract: A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.

Abstract: A boundary scan test system and a method thereof are disclosed. In the boundary scan test system, two ends of a first loopback line of each CPU test card are connected to another CPU test card and a boundary scan unit of a DIMM test card, respectively, and two ends of a second loopback line of each CPU test card are connected to boundary scan units of the different DIMM test cards, respectively, so as to generate boundary scan nets. A test control host executes a diagnosis program to select and trigger one of the boundary scan units of each boundary scan net, to output an excitation signal, and make the other boundary scan units receive corresponding response signals, and compare the response signals and corresponding expectation signals in each boundary scan net, so as to output a diagnosis result of each boundary scan net.

Abstract: A method and a device for generating boundary-scan interconnection lines are disclosed. In the method, the boundary scan test model is established according to boundary scan components and intermediate components on least one test card and a unit under test (UUT) board, and connection relationships therebetween; the boundary scan nets of the boundary scan test model are constructed; the boundary scan paths of each boundary scan net are generated, and a path establishment condition of each boundary scan path is obtained; and the boundary scan paths are filtered and integrated, and the filtered and integrated boundary scan paths are divided according to the path establishment conditions of filtered and integrated boundary scan paths, into subtests which each has at least one boundary-scan interconnection line. As a result, the accuracy and high coverage of a path search operation can be guaranteed.

Abstract: A pin conduction detection system for connector slot of circuit board, and a method thereof are disclosed. A connector slot detection circuit board is plugged on a connector slot of a to-be-detected circuit board, and the connector slot detection circuit boards including different types of connector slots are concatenated with each other. A TAP controller can set a JTAG chip of the connector slot detection circuit board to be in a boundary scan mode, and the JTAG chip can read at least one detection signal corresponding to at least one detection pin of the connector slot connector via one of a ADC, a microprocessor, and a switch, so that the TAP controller can perform an conduction detection on the pin of the connector slot corresponding to the detection signal. As a result, test efficiency and coverage rate of testing the connector slot of the circuit board can be improved.

Abstract: A test circuit board adapted to be used on memory slot is provided. Each memory slot of a board to be tested is connected to one test circuit board. A plurality of the test circuit boards form an in-series connection therebetween. A test access port (TAP) controller is connected electrically to the board to be tested and one of the test circuit boards so that the memory slots, which are connected to the test circuit boards, may be tested at the same time.

Abstract: A test circuit board adapted to be used on USB connector is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test circuit board adapted to be used on SATA connector is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test circuit board adapted to be used on memory slot is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.

Abstract: A test circuit board adapted to be used on PCI-E slot is provided. Two test circuit boards can be seriously connected with each other through a first JTAG connection interface and a second JTAG connection interface. Therefore, the efficiency of reducing TAPs of TAP controller and providing test signal coverage of all of test signals may be achieved.