Patents by Inventor Chang-seok Kang
Chang-seok Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190279999Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: May 20, 2019Publication date: September 12, 2019Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 10297543Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: June 13, 2017Date of Patent: May 21, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Publication number: 20190148400Abstract: A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole.Type: ApplicationFiled: September 3, 2018Publication date: May 16, 2019Inventors: Min-Yeong SONG, Chang-Seok KANG
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Patent number: 10199389Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.Type: GrantFiled: April 12, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
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Patent number: 10153292Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: GrantFiled: February 28, 2018Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
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Publication number: 20180261618Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: October 2, 2017Publication date: September 13, 2018Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Publication number: 20180190668Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
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Publication number: 20180166380Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: June 13, 2017Publication date: June 14, 2018Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 9972636Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: GrantFiled: June 19, 2017Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
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Patent number: 9905568Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: GrantFiled: August 30, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Son, Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Duk Lee, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Publication number: 20170294443Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
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Publication number: 20170229476Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.Type: ApplicationFiled: April 12, 2017Publication date: August 10, 2017Inventors: Jong-Won KIM, Chang-Seok KANG, Young-Woo PARK, Jae-Goo LEE, Jae-Duk LEE
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Patent number: 9716104Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: GrantFiled: January 5, 2016Date of Patent: July 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, HanMei Choi
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Patent number: 9646984Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.Type: GrantFiled: September 14, 2016Date of Patent: May 9, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
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Publication number: 20170092651Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.Type: ApplicationFiled: September 14, 2016Publication date: March 30, 2017Inventors: Jong-Won KIM, Chang-Seok KANG, Young-Woo PARK, Jae-Goo LEE, Jae-Duk LEE
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Publication number: 20170069637Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: ApplicationFiled: August 30, 2016Publication date: March 9, 2017Inventors: YONG-HOON SON, JONG-WON KIM, CHANG-SEOK KANG, YOUNG-WOO PARK, JAE-DUK LEE, KYUNG-HYUN KIM, BYEONG-JU KIM, PHIL-OUK NAM, KWANG-CHUL PARK, YEON-SIL SOHN, JIN-I LEE, WON-BONG JUNG
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Publication number: 20170040337Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: ApplicationFiled: January 5, 2016Publication date: February 9, 2017Inventors: Jong Won KIM, Seung Hyun LIM, Chang Seok KANG, Young Woo PARK, Dae Hoon BAE, Dong Seog EUN, Woo Sung LEE, Jae Duk LEE, Jae Woo LIM, HanMei CHOI
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Patent number: 9431418Abstract: A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.Type: GrantFiled: April 28, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Jung, Chang-Seok Kang, Min-Yong Lee, Sang-Woo Jin
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Patent number: 9349879Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.Type: GrantFiled: November 26, 2014Date of Patent: May 24, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Hyung Kim, Chang-Seok Kang, Sung-Il Chang, Jung-Dal Choi
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Patent number: 9299446Abstract: A nonvolatile memory device includes: a plurality of cell strings disposed on a substrate, wherein at least one of the plurality of cell strings comprises a plurality of cell transistors and at least one ground select transistor stacked in a direction substantially perpendicular to the substrate, and the substrate and a channel region of the plurality of cell strings have a same conductivity type; a substrate bias circuit configured to provide an erase voltage to the substrate in an erase operation; and a ground select line voltage generator configured to provide a ground select line saturation voltage to the at least one ground select transistor in the erase operation.Type: GrantFiled: June 13, 2014Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-hyung Kim, Chang-seok Kang, Young-suk Kim