Patents by Inventor Chang-seong Jeon

Chang-seong Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867857
    Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Seong Jeon, Seung-Hun Shin, Jae-Kyung Yoo, Teak-Hoon Lee
  • Publication number: 20200098635
    Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.
    Type: Application
    Filed: August 13, 2019
    Publication date: March 26, 2020
    Inventors: CHANG-SEONG JEON, SEUNG-HUN SHIN, JAE-KYUNG YOO, TEAK-HOON LEE
  • Publication number: 20160372447
    Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Hye-young JANG, Chang-Seong JEON, CHAJEA JO, Taeje CHO
  • Patent number: 9461029
    Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 4, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-young Jang, Chang-Seong Jeon, Chajea Jo, Taeje Cho
  • Patent number: 9245787
    Abstract: Apparatuses of manufacturing semiconductor packages are provided. An apparatus includes a chuck having a body, a porous plate disposed on the body, and a buffer pad disposed on the plate to provide a place on which a plurality of chips are loaded. The buffer pad has elasticity greater than the plate. The apparatus also includes a vacuum part supplying vacuum to the chuck so that the plurality of chips are sucked onto the buffer pad. Methods of manufacturing semiconductor packages using the apparatus are also provided.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: January 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Seong Jeon, Sangwook Park, TeakHoon Lee, Ilyoung Han
  • Publication number: 20150380394
    Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
    Type: Application
    Filed: June 19, 2015
    Publication date: December 31, 2015
    Inventors: Hye-young JANG, Chang-Seong JEON, CHAJEA JO, Taeje CHO
  • Patent number: 9177942
    Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonkeun Kim, In-Young Lee, Chang-Seong Jeon, Taeje Cho
  • Patent number: 9136260
    Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
  • Patent number: 9082871
    Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Jun Park, Won-Keun Kim, Teak-Hoon Lee, Chang-Seong Jeon, Young-Kun Jee
  • Publication number: 20150155259
    Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.
    Type: Application
    Filed: February 11, 2015
    Publication date: June 4, 2015
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Gi-Jun PARK, Won-Keun KIM, Teak-Hoon LEE, Chang-Seong JEON, Young-Kun JEE
  • Patent number: 8987904
    Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi-Jun Park, Won-Keun Kim, Teak-Hoon Lee, Chang-Seong Jeon, Young-Kun Jee
  • Publication number: 20150069635
    Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.
    Type: Application
    Filed: August 19, 2014
    Publication date: March 12, 2015
    Inventors: Wonkeun KIM, In-Young LEE, Chang-Seong JEON, Taeje CHO
  • Publication number: 20140196280
    Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Chang-Seong JEON, Ho-Geon SONG, Mitsuo UMEMOTO, Sang-Sick PARK
  • Publication number: 20140154839
    Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 5, 2014
    Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
  • Patent number: 8697494
    Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Chang-Seong Jeon, Ho-Geon Song, Mitsuo Umemoto, Sang-Sick Park
  • Patent number: 8637350
    Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
  • Patent number: 8637989
    Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
  • Publication number: 20140008794
    Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.
    Type: Application
    Filed: May 23, 2013
    Publication date: January 9, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Gi-Jun PARK, Won-Keun KIM, Teak-Hoon LEE, Chang-Seong JEON, Young-Kun JEE
  • Publication number: 20130149817
    Abstract: A fabricating method of a semiconductor device may include forming a semiconductor die on a supporting wafer, and picking up the die from the wafer by attaching to the die a transfer unit, the transfer unit including a head unit configured to enable twisting movement, and performing the twisting movement. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer; and picking up the first semiconductor device from the wafer, moving the first semiconductor device onto a second semiconductor device, and bonding the first semiconductor device to the second semiconductor device while maintaining the first semiconductor device oriented so that a surface faces upwardly. A fabricating method of a semiconductor device may include forming a first semiconductor device on a supporting wafer, attaching to the first semiconductor device a transfer unit configured to enable twisting movement, and performing the twisting movement.
    Type: Application
    Filed: July 26, 2012
    Publication date: June 13, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Seong JEON, Sang-Sick PARK, Sang-Wook PARK, Teak-Hoon LEE, Kwang-Chul CHOI
  • Publication number: 20120313332
    Abstract: Apparatuses of manufacturing semiconductor packages are provided. An apparatus includes a chuck having a body, a porous plate disposed on the body, and a buffer pad disposed on the plate to provide a place on which a plurality of chips are loaded. The buffer pad has elasticity greater than the plate. The apparatus also includes a vacuum part supplying vacuum to the chuck so that the plurality of chips are sucked onto the buffer pad. Methods of manufacturing semiconductor packages using the apparatus are also provided.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 13, 2012
    Inventors: Chang-Seong Jeon, Sangwook Park, TeakHoon Lee, Ilyoung Han