Patents by Inventor Chang-Woo Oh

Chang-Woo Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7265031
    Abstract: An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: September 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe
  • Publication number: 20070184611
    Abstract: According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.
    Type: Application
    Filed: April 3, 2007
    Publication date: August 9, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe
  • Patent number: 7247896
    Abstract: A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: July 24, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Jeong-Dong Choe
  • Publication number: 20070141796
    Abstract: Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.
    Type: Application
    Filed: October 30, 2006
    Publication date: June 21, 2007
    Inventors: Chang-woo Oh, Sung-hwan Kim, Dong-gun Park, Dong-won Kim
  • Publication number: 20070128779
    Abstract: Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 7, 2007
    Inventors: Chang-Woo Oh, Sung-Hwan Kim, Dong-Gun Park
  • Publication number: 20070122979
    Abstract: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 31, 2007
    Inventors: Chang-Woo Oh, Ki-Whan Song
  • Patent number: 7214987
    Abstract: According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: May 8, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Jeong-Dong Choe
  • Publication number: 20070063263
    Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
    Type: Application
    Filed: November 20, 2006
    Publication date: March 22, 2007
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Patent number: 7161206
    Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: January 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Publication number: 20060289907
    Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
    Type: Application
    Filed: August 31, 2006
    Publication date: December 28, 2006
    Inventors: Sung-Min Kim, Dong-Gun Park, Sung-Young Lee, Hye-Jin Cho, Eun-Jung Yun, Shin-Ae Lee, Chang-Woo Oh, Jeong-Dong Choe
  • Patent number: 7122431
    Abstract: Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-Gun Park, Sung-Young Lee, Hye-Jin Cho, Eun-Jung Yun, Shin-Ae Lee, Chang-Woo Oh, Jeong-Dong Choe
  • Publication number: 20060186460
    Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.
    Type: Application
    Filed: December 13, 2005
    Publication date: August 24, 2006
    Inventors: Byung-yong Choi, Chang-woo Oh, Dong-gun Park, Dong-won Kim, Yong-kyu Lee
  • Publication number: 20060154410
    Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 13, 2006
    Inventors: Byung-yong Choi, Chang-woo Oh, Dong-gun Park, Dong-won Kim
  • Publication number: 20060131666
    Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
    Type: Application
    Filed: September 30, 2005
    Publication date: June 22, 2006
    Inventors: Ming Li, Dong-Uk Choi, Chang-Woo Oh, Dong-Won Kim, Min-Sang Kim, Sung-Hwan Kim, Kyoung-Hwan Yeo
  • Publication number: 20060029887
    Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.
    Type: Application
    Filed: March 30, 2005
    Publication date: February 9, 2006
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Ming Li, Sung-hwan Kim
  • Publication number: 20060022268
    Abstract: A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Inventors: Chang-woo Oh, Dong-gun Park, Dong-won Kim, Sung-dae Suk
  • Publication number: 20050280102
    Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 22, 2005
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Dong-Uk Choi, Kyoung-Hwan Yeo
  • Publication number: 20050272192
    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.
    Type: Application
    Filed: December 23, 2004
    Publication date: December 8, 2005
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Publication number: 20050269629
    Abstract: A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
    Type: Application
    Filed: March 21, 2005
    Publication date: December 8, 2005
    Inventors: Chul Lee, Min-Sang Kim, Dong-gun Park, Choong-ho Lee, Chang-woo Oh, Jae-man Yoon, Dong-won Kim, Jeong-dong Choe, Ming Li, Hye-jin Cho
  • Publication number: 20050263795
    Abstract: In a method of forming a semiconductor device having an improved channel layer, the channel layer is formed on a surface of a semiconductor substrate and comprises a material of high carrier mobility such as silicon germanium (SiGe), germanium (Ge) and silicon carbide (SiC) using a selective epitaxial growth process. A gate insulation layer and a gate electrode are formed on the channel layer. Accordingly, a driving current of the semiconductor device increases to thereby improve operation characteristics.
    Type: Application
    Filed: May 24, 2005
    Publication date: December 1, 2005
    Inventors: Jeong-Dong Choi, Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim