Abstract: A method for manufacturing a semiconductor device comprises forming a SEG layer in a bottom of a storage node contact hole, and forming a spacer at a sidewall of a storage node contact hole and a bit line contact hole, thereby preventing expansion of the bottom of the bit line contact hole. Also, the method prevents a short phenomenon of a bit line contact plug and a recess gate, thereby improving an insulating characteristic of the device. The thickness of the spacer of the sidewall of the recess gate can be increased to protect the recess gate.

Abstract: A method for manufacturing a semiconductor device is capable of increasing the size of a landing plug without loss of an insulating film separating the landing plug, and may be advantageously used for reducing contact resistance by enlarging a landing plug contact hole without causing the loss of the insulating film due to a cleaning solution during a wet cleaning process. The semiconductor device manufacturing method includes the steps of: forming a gate over a semiconductor substrate and forming an interlayer insulating film filling spaces between the gates; selectively etching the interlayer insulating film to form a landing plug contact hole; forming a primary landing plug filling the landing plug contact hole preferably by a selective epitaxial growth method; forming, over the gate, a buffer dielectric film of an over-hang structure; and forming, over the primary landing plug, a secondary landing plug as a conductive film.

Abstract: A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer is formed over the gate spacer and a sidewall of the recess. An insulating film is formed over the semiconductor substrate. The insulating film is selectively etched to form a landing plug contact hole. A conductive layer in the landing plug contact hole is filled to form a landing plug.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a primary storage node contact plug at an upper part of the exposed landing plug at a lower part of the storage node contact hole; and filling the storage node contact hole with a conductive film to form a secondary storage node contact plug. In result, the size of a storage node contact may be increase to cause the contact resistance to decrease, without any loss of the interlayer insulating film to a cleaning solution.

Abstract: A temperature control system for a mold includes a circulation pipe provided in the mold, a heating water circulation section to provide heating water to the circulation pipe to pre-heat the mold, a cooling water circulation section to provide cooling water to the circulation pipe to cool the mold, and a compressed air circulation section to provide compressed air to the circulation pipe to eject remaining heating water or cooling water within the circulation pipe. The compressed air circulation section is adapted to supply the compressed air to the circulation pipe to eject remaining fluid within the circulation pipe before heating water or cooling water is provided to the circulation pipe.

Abstract: Disclosed is a manufacturing method of a keypad for a mobile phone and the keypad manufactured thereby, in which a vacuum deposition layer and a cellophane paper are attached to a lower surface of a key in the keypad.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: An insulation layer including a landing plug is formed over a substrate. An amorphous carbon hard mask is formed over a certain portion of the insulation layer. The insulation layer is etched using the amorphous carbon hard mask to form a storage node contact hole exposing the landing plug. A conductive material is formed in the storage node contact hole to form a storage node contact plug. Other embodiments are also described.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern having a double-layer hard mask including a nitride-based layer and an amorphous carbon-based layer, forming a planarized insulation layer filled between the bit line patterns, the planarized insulation layer flush with the nitride-based layer, forming line type storage node contact masks over predetermined portions of the planarized insulation layer, etching the planarized insulation layer to form storage node contact holes each having a top portion which is wider than a bottom portion, forming storage node contact spacers in a double layer structure on sidewalls of the storage node contact holes, and forming storage node contacts filling the storage node contact holes.

Abstract: The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract: Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.

Abstract: A method for forming a contact hole in a semiconductor device includes preparing a substrate including a bottom structure; forming an insulation layer such that the insulation layer covers the bottom structure; forming a silicon-rich oxynitride layer on the insulation layer; forming a photoresist pattern on the silicon-rich oxynitride layer; etching the silicon-rich oxynitride layer using the photoresist pattern as an etch mask, thereby obtaining hard masks; and etching the insulation layer using the photoresist pattern and the hard masks as an etch mask to form a contact hole exposing a portion of the bottom structure.

Abstract: A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Abstract: Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: The present invention relates to a method for fabricating a semiconductor device capable of improving an overlap margin that occurs when forming a conductive pattern, such as a bit line or a bit line contact. In order to achieve this effect, the method for fabricating a semiconductor device includes the steps of: forming a plug passing through an insulation layer to be contacted with a substrate board; forming a planarization insulation layer on an entire surface including the plug so as to cover defects appeared at a surface of the plug; forming a protective insulation layer on the planarization insulation layer for preventing losses of the planarization insulation layer resulted from a subsequent cleaning process; performing a process with an etchant; and forming a conductive layer contacted to the plug by passing through the protective insulation layer and the planarization insulation layer.