Patents by Inventor Changhong Dai

Changhong Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200294285
    Abstract: A non-transitory computer-readable medium stores instructions readable and executable by a workstation (18) including at least one electronic processor (20) to perform an image reconstruction method (100). The method includes: operating a positron emission tomography (PET) imaging device (12) to acquire imaging data on a frame by frame basis for frames along an axial direction with neighboring frames overlapping along the axial direction wherein the frames include a frame (k), a preceding frame (k?1) overlapping the frame (k), and a succeeding frame (k+1) overlapping the frame (k); reconstructing an image of the frame (k) using imaging data from the frame (k), the preceding frame (k?1), and the succeeding frame (k+1).
    Type: Application
    Filed: October 19, 2018
    Publication date: September 17, 2020
    Inventors: Xiyun SONG, Andriy ANDREYEV, Chuanyong BAI, Jinghan YE, Chi-Hua TUNG, Bin ZHANG, Xiangyu WU, Changhong DAI, Tianrui GUO, Zhiqiang HU
  • Patent number: 10438379
    Abstract: A system (10) and a method (100) iteratively reconstruct an image of a target volume of a subject. In each iteration of a plurality of iterations, an estimate image of the target volume (54) is forward projected (58) and compared (62) to received event data (44) to determine a discrepancy (64). The discrepancy (64) is back projected (66) and the back projection (68) updates (70) the estimate image (54). In at least one iteration, the estimate image (54) is filtered (52) in the image domain prior to being back projected.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 8, 2019
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Xiyun Song, Jinghan Ye, Zhiqiang Hu, Changhong Dai, Varun Verma, Chi-Hua Tung
  • Publication number: 20180066470
    Abstract: Vacuum glass includes a piece of upper glass, a piece of lower glass, and a closed vacuum layer sandwiched between the upper class and the lower glass, the peripheries of the upper glass and the lower glass are in seal connection using two or more layers of sealing material, the upper glass and the lower glass are convex glass or flat glass, convex surfaces of the convex glass face outward, and supports are disposed between two pieces of flat glass. The manufacturing method of the vacuum glass is simple, the prepared vacuum glass and tempered vacuum glass solve the defects in the prior art, can ensure the airtightness and service life of the vacuum glass, and are suitable for mechanization, automation, and mass production.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 8, 2018
    Inventor: Changhong DAI
  • Patent number: 9688575
    Abstract: A low pressure air or vacuum glass and manufacturing method thereof, the low pressure air or vacuum glass comprising upper glass and lower glass; the upper glass and the lower glass are flat glass or convex glass; the peripheries of the upper glass and the lower glass are provided with an edge sealing bar frame and/or an edge sealing groove, and are welded together via a low temperature glass solder, thus forming a closed low pressure air layer or vacuum layer therebetween. The low pressure or vacuum glass is of simple manufacturing process, low cost, high production efficiency, reliable sealing connection, and good sealing effect.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 27, 2017
    Inventor: Changhong Dai
  • Publication number: 20160350945
    Abstract: A system (10) and a method (100) iteratively reconstruct an image of a target volume of a subject. In each iteration of a plurality of iterations, an estimate image of the target volume (54) is forward projected (58) and compared (62) to received event data (44) to determine a discrepancy (64). The discrepancy (64) is back projected (66) and the back projection (68) updates (70) the estimate image (54). In at least one iteration, the estimate image (54) is filtered (52) in the image domain prior to being back projected.
    Type: Application
    Filed: February 18, 2015
    Publication date: December 1, 2016
    Applicant: Koninklijke Philips N.V.
    Inventors: Xiyun SONG, Jinghan YE, Zhiqiang HU, Changhong DAI, Varun VERMA, Chi-Hua TUNG
  • Publication number: 20150317441
    Abstract: A nuclear medicine scanner system (1) includes an intelligent scheduler (2) which schedules a plurality of patients, each for an ordered nuclear medicine scanning procedure with a nuclear medicine scanning device (4) based on data mined from prior patients with like scanning procedures and in a time window which minimizes the patient dose.
    Type: Application
    Filed: December 2, 2013
    Publication date: November 5, 2015
    Inventors: Benjamin LORMAN, Yu-Lung HSIEH, Varun VERMA, Chi-Hua TUNG, Changhong DAI
  • Publication number: 20150024151
    Abstract: A low pressure air or vacuum glass and manufacturing method thereof, the low pressure air or vacuum glass comprising upper glass and lower glass; the upper glass and the lower glass are flat glass or convex glass; the peripheries of the upper glass and the lower glass are provided with an edge sealing bar frame and/or an edge sealing groove, and are welded together via a low temperature glass solder, thus forming a closed low pressure air layer or vacuum layer therebetween. The low pressure or vacuum glass is of simple manufacturing process, low cost, high production efficiency, reliable sealing connection, and good sealing effect.
    Type: Application
    Filed: March 21, 2013
    Publication date: January 22, 2015
    Inventor: Changhong Dai
  • Publication number: 20140107476
    Abstract: A PET apparatus includes a detector array including individual detectors which receive radiation events from an imaging region. A movement controller controls at least one of relative longitudinal movement between a subject support and the detector array and circumferential movement between the detector array and the subject. A time stamp processor assigns a time stamp to each received radiation event. A list mode event storage buffer stores time stamped events. An event verification processor screens for coincidentally received radiation events, locations at which each pair of corresponding coincidentally received events defining a line of response. A reconstruction processor reconstructs valid events into an image representation of the imaging region.
    Type: Application
    Filed: June 1, 2012
    Publication date: April 17, 2014
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Chi-Hua Tung, Bin Zhang, Changhong Dai
  • Patent number: 7509247
    Abstract: A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may include essential circuit prints and backfill circuit prints. Various unknowns may be eliminated between essential circuit prints of the computational model. The unknowns to be eliminated may include volume unknowns and backfill circuit-print unknowns. The numerical system formed by circuit-print unknowns may be divided into a plurality of blocks. The blocks may be solved in turn. One block may be solved by projecting the contributions from other blocks to this block. The solution of the one block may be translated to other blocks to solve unknowns therein. The computational model may then be solved to determine electromagnetic and circuit characteristics of the structure.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: March 24, 2009
    Assignee: Intel Corporation
    Inventors: Dan Jiao, Changhong Dai
  • Patent number: 7411269
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Patent number: 7410858
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Patent number: 7289945
    Abstract: In one embodiment, an interconnect structure may be analyzed to determine electromagnetic characteristics of the structure by identifying structure seeds corresponding to the structure; modeling the structure seeds to obtain field patterns; and processing the field patterns to obtain the electromagnetic characteristics.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Dan Jiao, Mohiuddin Mazumder, Changhong Dai
  • Publication number: 20070013023
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Application
    Filed: September 22, 2006
    Publication date: January 18, 2007
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Publication number: 20070005324
    Abstract: An arrangement is provided for using s-parameters to obtain characteristics of a device under test (“DUT”) between a number of selected observation locations. The DUT may be represented by a network of models such as lumped device models and transmission line models. S-parameters between the selected nodes may be measured based on the DUT representation at a plurality of frequency points. The measured s-parameters may be converted into their precision space (“p-space”) representations, which may then be submitted to a simulator to obtain the DUT characteristics at the selected observation nodes.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Jian Gong, Changhong Dai
  • Publication number: 20070005325
    Abstract: An arrangement is provided for using a precision space (“p-space”) to represent s-parameters when analyzing/simulating a circuit/network. The p-space is one dimensional with a value range corresponding to the value range of s-parameters. The p-space is divided into multiple slots where the number of slots may depend on the permissible precision of s-parameter values. A mapping relationship between s-parameters and p-space slots may be obtained by partitioning an s-parameter matrix. Based on the mapping relationship, p-space representations of original s-parameters may be generated through a forward projection process from s-parameters in a two-dimensional matrix to the one-dimensional p-space. During the simulation process, a p-space representation may be projected back to original s-parameters in a matrix based on the mapping relationship.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Jian Gong, Changhong Dai
  • Publication number: 20060220147
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Application
    Filed: May 19, 2006
    Publication date: October 5, 2006
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Publication number: 20060224373
    Abstract: A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may include essential circuit prints and backfill circuit prints. Various unknowns may be eliminated between essential circuit prints of the computational model. The unknowns to be eliminated may include volume unknowns and backfill circuit-print unknowns. The numerical system formed by circuit-print unknowns may be divided into a plurality of blocks. The blocks may be solved in turn. One block may be solved by projecting the contributions from other blocks to this block. The solution of the one block may be translated to other blocks to solve unknowns therein. The computational model may then be solved to determine electromagnetic and circuit characteristics of the structure.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 5, 2006
    Inventors: Dan Jiao, Changhong Dai
  • Publication number: 20050179109
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Application
    Filed: March 28, 2005
    Publication date: August 18, 2005
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Patent number: 6876053
    Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: April 5, 2005
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
  • Publication number: 20040082230
    Abstract: In one embodiment, an interconnect structure may be analyzed to determine electromagnetic characteristics of the structure by identifying structure seeds corresponding to the structure; modeling the structure seeds to obtain field patterns; and processing the field patterns to obtain the electromagnetic characteristics.
    Type: Application
    Filed: October 28, 2002
    Publication date: April 29, 2004
    Inventors: Dan Jiao, Mohiuddin Mazumder, Changhong Dai