Patents by Inventor Chao-Ching Cheng

Chao-Ching Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359737
    Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220352312
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220352366
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li CHIANG, Yu-Chao LIN, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung-Ying LEE
  • Publication number: 20220344357
    Abstract: A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yan Chung, Chao-Ching Cheng
  • Patent number: 11482571
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen
  • Publication number: 20220335983
    Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Hung-Li CHIANG, Yu-Sheng CHEN, Chao-Ching CHENG, Tzu-Chiang CHEN
  • Publication number: 20220336681
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hou-Yu CHEN, Chao-Ching CHENG, Tzu-Chiang CHEN, Yu-Lin YANG, I-Sheng CHEN
  • Publication number: 20220336738
    Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen
  • Patent number: 11476356
    Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220285612
    Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220285495
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Application
    Filed: June 18, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Publication number: 20220285345
    Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.
    Type: Application
    Filed: June 23, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Patent number: 11437468
    Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 6, 2022
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11417729
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220231153
    Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the etch stop layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lu, Tzu Ang Chao, Chao-Ching Cheng, Lain-Jong Li
  • Publication number: 20220231030
    Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Chih-Chieh Yeh
  • Patent number: 11393925
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Yu-Chao Lin, Chao-Ching Cheng, Tzu-Chiang Chen, Tung-Ying Lee
  • Patent number: 11380803
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hou-Yu Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 11380369
    Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Yu-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen
  • Patent number: 11349069
    Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li