Patents by Inventor Chao-Fu Weng

Chao-Fu Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040183195
    Abstract: The present invention relates to an under bump metallurgy layer, comprising an adhesion layer, a barrier layer and a wetting-barrier layer. The adhesion layer, the barrier layer and the wetting-barrier layer are arranged sequentially on the pad of the chip, and the wetting-barrier layer is disposed between the barrier layer and the bump. The wetting-barrier layer, containing nickel, can improve the bonding ability between the pad and the bump. Also, the invention relates to a flip chip structure including at least a chip, a plurality of bumps and the under bump metallurgy mentioned above.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 23, 2004
    Inventors: Min-Lung Huang, Chi-Long Tsai, Chao-Fu Weng, Ching-Huei Su
  • Publication number: 20040185649
    Abstract: A wafer bumping process is disclosed. A wafer having a plurality of bonding pads formed thereon is provided. A first under bump metallurgy layer is formed to cover the bonding pads. A first patterned photoresist layer having a plurality of first openings is formed on the first under bump metallurgy layer, wherein a portion of the first under bump metallurgy layer is exposed within the first openings. A second under bump metallurgy layer is formed within the first openings, wherein the second under bump metallurgy layer is much thicker than the first under bump metallurgy layer. A second patterned photoresist layer having a plurality of second openings is formed on the first patterned photoresist layer, wherein the second openings being larger than the first openings.
    Type: Application
    Filed: March 19, 2004
    Publication date: September 23, 2004
    Inventors: MIN-LUNG HUANG, CHI-LONG TSAI, CHAO-FU WENG, CHING-HUEI SU
  • Patent number: 6756256
    Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: June 29, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20040114294
    Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.
    Type: Application
    Filed: August 15, 2003
    Publication date: June 17, 2004
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20040112944
    Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.
    Type: Application
    Filed: August 14, 2003
    Publication date: June 17, 2004
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Publication number: 20040110364
    Abstract: A method for making UBM (Under Bump Metallurgy) pads and bumps on a wafer is disclosed. Openings are formed in a photoresist layer for forming bumps, a positive liquid photoresist is provided into the openings of the photoresist layer for forming bumps. The positive liquid photoresist is exposed and developed to modify the openings of the photoresist layer. Thus, bumps formed in the modified openings have precise bonding areas on the UBM layer. Using the bumps as a mask, UBM pads under the bumps are formed by etching the UBM layer, so that the reflowed bumps have an uniform height.
    Type: Application
    Filed: November 20, 2003
    Publication date: June 10, 2004
    Inventors: Chi-Long Tsai, Min-Lung Huang, Chao-Fu Weng, En-Chieh Wu, Yang Hong-Zen
  • Patent number: 6743707
    Abstract: The present invention provides a bump fabrication process. A wafer is provided with a patterned photoresist layer formed on the wafer. The patterned photoresist layer has a plurality of openings, corresponding to bonding pads. A conductive layer is formed on the photoresist layer and the exposed bonding pads. Afterwards, a sticker film is the provided to lift off the conductive layer on the photoresist layer, while the conductive layer within the openings is not removed. A solder paste is filled into the openings. A reflow step is performed to turn the filled solder paste into globular bumps. At last, the protoresist layer is removed.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: June 1, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Patent number: 6732912
    Abstract: A solder ball attaching process for attaching solder balls to a wafer is provided. First, an under-ball-metallurgy layer is formed on the active surface of the wafer. Patterned masking layers are sequentially formed over the active surface of the wafer. The masking layers together form a step opening structure that exposes the under-ball-metallic layer. A solder ball is placed on the uppermost masking layer and allowed to roll so that the solder ball drops into the step opening structure by gravity. A reflow process is conducted to join the solder ball and the under-ball-metallurgy layer together. Finally, various masking layers are removed to expose the solder ball on the bonding pad of the wafer.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: May 11, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6723630
    Abstract: A solder ball fabrication process for forming solder balls over a wafer having an active layer is provided. A plurality of patterned solder mask layers is sequentially formed over the active surface of the wafer. Each patterned solder mask layer has at least an opening that exposes a solder ball pad on the wafer. The opening of the patterned solder mask layers further away from the solder ball pad is larger in diameter than the opening of the patterned solder mask close to the solder ball pad. Solder material is deposited into the openings and a reflow process is conducted to melt the solder material together so that a solder ball is formed over the solder ball pad.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: April 20, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Patent number: 6720244
    Abstract: A bump fabrication method is described. The method comprises the steps of providing a wafer having an active surface and a plurality of bonding pads formed on the active surface; respectively forming an under bump metallurgy layer onto the bonding pads, wherein the under bump metallurgy layer includes at least a wetting layer having an oxidized region and positioned at a top layer of the under bump metallurgy layer; patterning a masking layer on the active surface wherein the masking layer is provided with a plurality of openings to expose the wetting layers; removing the oxidized region of the wetting layer using ionic bombardment; fully forming a flux film on the active layer, wherein at least a portion of the flux film covers onto the wetting layer; filling a solder paste into the openings; performing a re-flow process to form a plurality of bumps after the solder paste melts so that the flux film removes the oxidized region of the wetting layer; and removing the masking layer.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: April 13, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6720243
    Abstract: A method of fabricating bumps is disclosed. In the present method, prior to forming solder, layer pattern, the wetting layer and the barrier layer are removed, and after a solder layer pattern is formed, only the exposed adhesion layer is removed. The method can avoide etching the solder layer pattern in the course of etching the solder layer and the barrier layer, and therefore the volume of the required solder layer pattern can be maintained. Thus, the height of the bump after the re-flow process is maintained at an appropriate range and the required bonding force between the bump and the under ball metallurgy layer pattern can be maintained so as to improve the reliability.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: April 13, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao-Fu Weng
  • Patent number: 6716739
    Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-ball metallic layer is formed over the active surface of the wafer. A second under-ball metallic layer is formed over the first under-ball metallic layer. A portion of the second under-ball metallic layer is removed to expose the first under-ball metallic layer. A plurality of solder blocks is implanted over the second under-ball metallic layer. A reflux operation is conducted and then the exposed first under-ball metallic layer is removed so that only the first under-ball metallic layer underneath the second under-ball metallic layer remains.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: April 6, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6713320
    Abstract: A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 30, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6673711
    Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: January 6, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Patent number: 6664128
    Abstract: The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: December 16, 2003
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20030189260
    Abstract: A flip-chip bonding structure suited for bonding a first connect pad and a second connect pad. The flip-chip bonding structure includes a metal layer, a bump and an adhesion body. The metal layer is placed on the first connect pad. The bump, lead-free material, is placed on the metal layer. The adhesion body, made of lead-free material, is placed on the bump and is bonded onto the second connect pad.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 9, 2003
    Inventors: HO-MING TONG, CHUN-CHI LEE, JEN-KUANG FANG, MIN-LUNG HUANG, CHING-HUEI SU, CHAO-FU WENG
  • Publication number: 20030189261
    Abstract: An under-ball-metallurgy layer over a contact pad is provided. The contact pad and corresponding contact surface of the under-bump-metallurgy layer are made of copper. The under-ball-metallurgy layer is constructed from a stack of metallic layers selected from a group consisting of titanium/copper, titanium-tungsten alloy/copper, tantalum/copper, titanium/titanium-nitride compound/copper, tantalum/tantalum-nitride compound/copper, tantalum/nickel-vanadium alloy/copper, tantalum/nickel/copper, copper/nickel-vanadium alloy/copper, titanium/nickel/copper, copper/chromium-copper alloy/copper, or chromium-copper alloy/chromium/chromium-copper alloy/copper.
    Type: Application
    Filed: March 11, 2003
    Publication date: October 9, 2003
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Ching-Huei Su, Chao-Fu Weng
  • Publication number: 20030189249
    Abstract: A chip structure having a chip, an adhesion layer, and a metal layer. The chip has an active surface and many conductive pads. The conductive pads are disposed on the active surface, wherein the conductive pads are made of copper. The adhesion layer is directly formed on the conductive pads, wherein the material of the adhesion layer includes copper. The metal layer is formed on the adhesion layer, wherein the material of the metal layer includes copper.
    Type: Application
    Filed: March 11, 2003
    Publication date: October 9, 2003
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Ching-Huei Su, Chao-Fu Weng
  • Patent number: 6617237
    Abstract: A lead-free solder bump fabrication process for producing a plurality of lead-free solder bumps over a wafer is provided. The lead-free solder bump fabrication process includes forming a lead-free pre-formed solder bump over each bonding pad on the wafer and then forming a patterned solder mask layer over the active surface of the wafer. The openings in the solder mask layer expose the respective lead-free pre-formed solder bumps on the wafer. Thereafter, lead-free solder material is deposited into the opening. The material composition of the lead-free solder material differs from the material composition of the lead-free pre-formed solder bump. A reflow process is conducted so that the lead-free pre-formed solder bump fuses with the lead-free solder material to form a lead-free solder bump. Finally, the solder mask layer is removed.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: September 9, 2003
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20030166331
    Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at leastwith an opening that exposes the pre-formed bump.
    Type: Application
    Filed: February 10, 2003
    Publication date: September 4, 2003
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao