Patents by Inventor Chao-Fu Weng

Chao-Fu Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030155231
    Abstract: An electric field adjusting apparatus for adjusting electric field distribution inside an electroplating bath is provided. The electric field adjusting apparatus has a regulation plate with a plurality of evenly distributed through holes. A plurality of evenly distributed through holes with a smaller total through hole area is formed in the regulation plate that corresponds to an area of a plated film on a wafer that conducts a larger current during an electroplating process (close to the edge of the wafer). Meanwhile, a plurality of evenly distributed through holes with a larger total through hole area is formed in the regulation plate that corresponds to an area of the plated film on the wafer that conducts a smaller current during an electroplating process (close to the central region of the wafer). Furthermore, the total area of through holes around a particular location is inversely proportional to the current density in the plated film over the plating object.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventor: Chao-Fu Weng
  • Publication number: 20030146191
    Abstract: A method for etching a nickel-vanadium alloy is described. The etching of the nickel-vanadium alloy is conducted using an etchant that comprises sulfuric acid. Further, the etching rate of the nickel-vanadium alloy is controlled based on the electrolytic reaction between the etchant and the nickel-vanadium alloy thin film.
    Type: Application
    Filed: January 10, 2003
    Publication date: August 7, 2003
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Publication number: 20030129541
    Abstract: A redistribution process is described. A wafer is provided, wherein a first titanium layer, a first copper layer and a second titanium are sequentially formed over the surface of the wafer. The second titanium layer, the first copper layer and the first titanium layer are then defined to form a patterned trace layer. A patterned benzocyclobutene layer is then formed to expose the second titanium layer. The exposed second titanium layer is further removed to expose the first copper layer. Thereafter, a plurality of contacts is formed over the patterned benzocyclobutene layer and to connect with the first copper layer. Further, the wafer comprises a plurality of bonding pads, wherein each bonding pad is connected with each contact through the patterned trace layer.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 10, 2003
    Inventor: Chao-Fu Weng
  • Publication number: 20030127730
    Abstract: A chip structure with bumps comprising: a chip and at least a bump. The chip has an active surface and at least a bonding pad that is formed on the active surface. The bump is disposed on the bonding pad, and the bump comprises a medium layer, a bump body and a bump body passivation layer. The medium layer whose material includes zinc is disposed on the bonding pad. The bump body whose material includes nickel is disposed on the medium layer. The bump body passivation layer whose material includes gold covers the bump body except for a portion of the bump body that connects to the medium layer.
    Type: Application
    Filed: November 5, 2002
    Publication date: July 10, 2003
    Inventor: Chao-Fu Weng
  • Publication number: 20030129821
    Abstract: A method of fabricating bumps is disclosed. In the present method, prior to forming solder layer pattern, the wetting layer and the barrier layer are removed, and after a solder layer pattern is formed, only the exposed adhesion layer is removed. The method can avoide etching the solder layer pattern in the course of etching the solder layer and the barrier layer, and therefore the volume of the required solder layer pattern can be maintained. Thus, the height of the bump after the re-flow process is maintained at an appropriate range and the required bonding force between the bump and the under ball metallurgy layer pattern can be maintained so as to improve the reliability.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 10, 2003
    Inventor: Chao-Fu Weng
  • Publication number: 20030124833
    Abstract: The present invention provides a bump fabrication process. A wafer is provided with a patterned photoresist layer formed on the wafer. The patterned photoresist layer has a plurality of openings, corresponding to bonding pads. A conductive layer is formed on the photoresist layer and the exposed bonding pads. Afterwards, a sticker film is provided to lift off the conductive layer on the photoresist layer, while the conductive layer within the openings is not removed. A solder paste is filled into the openings. A reflow step is performed to turn the filled solder paste into globular bumps. At last, the photoresist layer is removed.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 3, 2003
    Inventors: Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yung-Chi Lee , Yu-Chen Chou