Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes word lines, channel layer, gate dielectric layers, a conductive pillar and a storage pillar. The word lines extend along a first direction over a substrate, and are vertically spaced apart from one another. The channel layers respectively line along a sidewall of one of the word lines. The gate dielectric layers respectively line between one of the word lines and one of the channel layers. The conductive pillar and the storage pillar penetrate through the channel layers. The storage pillar includes an inner electrode, a switching layer and an outer electrode. The switching layer wraps around the inner electrode. The outer electrode laterally surrounds the switching layer, and includes annulus portions vertically spaced apart from one another and each in lateral contact with a corresponding one of the channel layers.

Abstract: A memory device includes a multi-layer stack, a plurality of channel layers and a plurality of ferroelectric layers. The multi-layer stack is disposed on a substrate and includes a plurality of gate layers and a plurality of dielectric layers stacked alternately. The plurality of channel layers penetrate through the multi-layer stack and are laterally spaced apart from each other, wherein the plurality of channel layers include a first channel layer and a second channel layer, and a first electron mobility of the first channel layer is different from a second electron mobility of the second channel layer. Each of the plurality of channel layers are spaced apart from the multi-layer stack by one of the plurality of ferroelectric layers, respectively.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.

Abstract: A semiconductor package includes a processor die, a storage module and a package substrate. The storage module includes an array of cache units and an array of memory units stacked over one another, and electrically connected to the processor die, wherein the array of cache units is configured to hold copies of data stored in the array of memory units and frequently used by the processor die. The package substrate is on which the processor die and the storage module are disposed.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

Abstract: A memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.

Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.

Abstract: A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.