Patents by Inventor Chao-Sheng Cheng

Chao-Sheng Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134979
    Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
  • Patent number: 10304685
    Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 28, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chao-Sheng Cheng
  • Publication number: 20190051530
    Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.
    Type: Application
    Filed: August 14, 2017
    Publication date: February 14, 2019
    Inventor: Chao-Sheng Cheng
  • Patent number: 10068900
    Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin Yang, Chao-Sheng Cheng
  • Publication number: 20180240798
    Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region; HV gate structures formed in the HV region of the substrate; a HV dummy pattern disposed in the HV region, and the HV dummy pattern comprising at least a semiconductor portion and a dummy HM stack disposed on the semiconductor portion, wherein a height (hS) of the semiconductor portion of the HV dummy pattern is smaller than a height (hHV-g) of a HV gate electrode of one of the HV gate structures.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Chin Yang, Chao-Sheng Cheng
  • Patent number: 10056397
    Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 21, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chao-Sheng Cheng
  • Publication number: 20180166455
    Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.
    Type: Application
    Filed: February 8, 2018
    Publication date: June 14, 2018
    Inventor: Chao-Sheng Cheng
  • Patent number: 9929164
    Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chao-Sheng Cheng
  • Publication number: 20180012899
    Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.
    Type: Application
    Filed: August 10, 2016
    Publication date: January 11, 2018
    Inventor: Chao-Sheng Cheng
  • Patent number: 9570456
    Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 14, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Jen, Chao-Sheng Cheng
  • Publication number: 20170025429
    Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Po-Han Jen, Chao-Sheng Cheng
  • Patent number: 9041155
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
  • Patent number: 8729237
    Abstract: The present invention provides a polypeptide adjuvant composition with thermostability, which is designed from wild-type chicken interleikin-1? to construct a new chicken interleikin-1?, named CP-interleikin-1?. The CP-interleikin-1? having improved heat resistance keeps the original biological activity, and which helps to develop protein adjuvant with high efficiency and uses in medical application. The present invention also provides a method of manufacturing such polypeptide adjuvant composition.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 20, 2014
    Assignee: National Tsing Hua University
    Inventors: Hsien-Sheng Yin, Chao-Sheng Cheng
  • Publication number: 20140135479
    Abstract: The present invention provides a polypeptide adjuvant composition with thermostability, which is designed from wild-type chicken interleikin-1? to construct a new chicken interleikin-1?, named CP-interleikin-1?. The CP-interleikin-1? having improved heat resistance keeps the original biological activity, and which helps to develop protein adjuvant with high efficiency and uses in medical application. The present invention also provides a method of manufacturing such polypeptide adjuvant composition.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 15, 2014
    Applicant: National Tsing Hua University
    Inventors: Hsien-Sheng Yin, Chao-Sheng Cheng
  • Patent number: 8664705
    Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
  • Publication number: 20140008762
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng
  • Publication number: 20130320421
    Abstract: A MOS capacitor includes a substrate, a p-type MOS (pMOS) transistor positioned on the substrate, and an n-type MOS (nMOS) transistor positioned on the substrate. More important, the pMOS transistor and the nMOS transistor are electrically connected in parallel. The MOS transistor further includes a deep n-well that encompassing the pMOS transistor and the nMOS transistor.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventors: Kai-Ling Chiu, Chao-Sheng Cheng, Chih-Yu Tseng, Yu-Jen Liu
  • Patent number: 8558346
    Abstract: A semiconductor structure includes a first capacitor and a second capacitor. The first capacitor includes a plurality of first units and each first unit includes a plurality of first finger electrodes. The second capacitor includes a plurality of second units and each second unit includes a plurality of second finger electrodes. The first units and the second units are alternately arranged to form an array. The semiconductor structure further includes a plurality of first connecting lines and a plurality of second connecting lines being parallel with each other. The first connecting lines are electrically connected to the first finger electrodes, and the second connecting lines are electrically connected to the second finger electrodes. The first finger electrodes and its adjacent first connecting lines form a straight line, and the second finger electrodes and its adjacent second connecting lines form another straight line.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: October 15, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chao-Sheng Cheng, Kai-Ling Chiu, Chih-Yu Tseng