Abstract: Some embodiments relate to an integrated circuit including a plurality of floating diffusion regions ohmically connected to a common contact via a patterned conductive layer, obviating a need for individual contacts for each floating diffusion region. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a conductive layer that are stacked over one another in alternating fashion. A contact electrode is disposed over and in direct (e.g., direct and ohmic) contact with the conductive layer. The conductive layer is directly (e.g., directly and ohmically) connected to a respective surface of each of a plurality of floating diffusion regions. The respective surfaces connected by the conductive layer are co-planar with one another. Each floating diffusion region can be associated with a respective pixel of an array of pixels of an image sensor.

Abstract: In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A FDTI trench is formed from a frontside of a substrate between a first pixel region and a second pixel region and then filled to form a FDTI structure. A cap layer is formed over the FDTI structure overlying the first pixel region and the second pixel region of the substrate. A first photodiode is formed in the first pixel region and a second photodiode is formed in the second pixel region. A FD node is formed within the cap layer between the first pixel region and the second pixel region overlying the FDTI structure. The FD node may be shared by a group of pixel regions not separated by the FDTI structure, such that few metal contacts are needed and thus reduce parasitic capacitance issues of proximity metal contacts.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source/drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source/drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source/drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source/drain contact.

Abstract: A carrier including a bottom plate, an intermediate cover, and a top cover for manufacturing a memory device is introduced herein. A printed circuit board is disposed on the bottom plate, and memory elements are arranged and disposed on the PCB. The intermediate cover is used to press peripheral regions of the printed circuit board, and to expose the regions where the memory elements are formed on the printed circuit board. The printed circuit board is closely attached to a surface of the bottom plate by fixing the intermediate cover. The top cover is used to cover the memory elements formed on the printed circuit board after some manufacturing processes, and by exerting an external force, the formed memory elements are clamped down, so as to protect the memory elements from being affected by the printed circuit board in the following thermal process due to the thermal stress deformation.

Abstract: A carrier including a bottom plate, an intermediate cover, and a top cover for manufacturing a memory device is introduced herein. A printed circuit board is disposed on the bottom plate, and memory elements are arranged and disposed on the PCB. The intermediate cover is used to press peripheral regions of the printed circuit board, and to expose the regions where the memory elements are formed on the printed circuit board. The printed circuit board is closely attached to a surface of the bottom plate by fixing the intermediate cover. The top cover is used to cover the memory elements formed on the printed circuit board after some manufacturing processes, and by exerting an external force, the formed memory elements are clamped down, so as to protect the memory elements from being affected by the printed circuit board in the following thermal process due to the thermal stress deformation.