Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.

Abstract: The present disclosure provides a memory device and a manufacturing method of the memory device. The memory device includes: a substrate, a landing area over the substrate, a bottom electrode over the landing area, and a high-k layer over the bottom electrode, wherein the bottom electrode includes a lower portion over the landing area, a middle portion over the lower portion, and an upper portion over the middle portion, and the bottom electrode has a container-shaped profile.

Abstract: A battery pack electrically comprising a temperature terminal and is configured such that when an external device is electrically connected to the battery pack, the device can detect the temperature of the battery pack, and the battery pack is further configured to receive a PWM signal from the external device when in the electrical connection state, and, on the basis of the PWM signal, determine the type and/or operating state of the external device. Also disclosed, a power tool system comprising the battery pack, as well as a communication system for the battery pack and the system. With the battery pack and the power tool system, it is possible to perform both a temperature sampling function and a function of identifying external device information only by a temperature terminal of the battery pack, thus same have the advantages of a simple and compact structure and low cost.

Abstract: A system including a battery pack provided with a connecting terminal and a wireless communication module, the battery pack configured to establish an electrical connection and communication connection with a terminal device via the connecting terminal and configured to issue broadcast information via the wireless communication module, the broadcast information including identity information of the terminal device connected to the battery pack.

Abstract: The present disclosure provides a memory device and a manufacturing method of the memory device. The memory device includes: a substrate, a landing area over the substrate, a bottom electrode over the landing area, and a high-k layer over the bottom electrode, wherein the bottom electrode includes a lower portion over the landing area, a middle portion over the lower portion, and an upper portion over the middle portion, and the bottom electrode has a container-shaped profile.

Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.

Abstract: An electrical appliance assembly for multiclient networking, comprising an electrical appliance and a battery unit, wherein the electrical appliance is configured to obtain electric energy from the battery unit or provide electric energy to the battery unit, wherein the electrical appliance, as a first client, comprises a first communication interface and a second communication interface, wherein the first communication interface is configured to communicate with a peripheral device, and the second communication interface is configured to communicate with the battery unit. The battery unit, as a second client, comprises a third communication interface and a fourth communication interface, wherein the third communication interface is configured to communicate with a peripheral device, and the fourth communication interface is configured to communicate with the electrical appliance.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant.

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Abstract: In some examples, an electronic device includes an audio output device, an airflow generator to generate an airflow, and a system controller to control an operational speed of the airflow generator. The electronic device further includes an audio controller to generate a noise cancellation audio output based on an indicator of the operational speed of the airflow generator provided from the system controller to the audio controller, and send the noise cancellation audio output to the audio output device to mitigate noise produced by the airflow generator.