Abstract: Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Abstract: An embodiment for root cause analysis of computerized system anomalies is provided. The embodiment may include monitoring key performance indicators (KPIs) for a computerized system, wherein KPI values of the monitored KPIs form respective timeseries. The embodiment may include detecting an anomaly in the computerized system based on the monitored KPIs. The embodiment may include determining a troubleshooting time window extending over a given time period. The embodiment may include identifying a strict subset of the monitored KPIs based on portions of the respective timeseries spanning the given time period. The strict subset comprises abnormal KPIs (aKPIs) and potential explanatory KPIs (xKPIs). The embodiment may include obtaining a causal graph of vertices mapping KPIs of the strict subset by running a causality algorithm to evaluate weights of directed edges connecting the vertices and accordingly obtain one or more directed paths. The embodiment may include returning the obtained causal graph.

Abstract: In an approach for constructing an ensemble model from a set of base learners, a processor performs a plurality of boosting iterations, where: at each boosting iteration of the plurality of boosting iterations, a base learner is selected at random from a set of base learners, according to a sampling probability distribution of the set of base learners, and trained according to a training dataset; and the sampling probability distribution is altered: (i) after selecting a first base learner at a first boosting iteration of the plurality of boosting iterations and (ii) prior to selecting a second base learner at a final boosting iteration of the plurality of boosting iterations. A processor constructs an ensemble model based on base learners selected and trained during the plurality of boosting iterations.

Abstract: A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.

Abstract: An embodiment for root cause analysis of computerized system anomalies is provided. The embodiment may include monitoring key performance indicators (KPIs) for a computerized system, wherein KPI values of the monitored KPIs form respective timeseries. The embodiment may include detecting an anomaly in the computerized system based on the monitored KPIs. The embodiment may include determining a troubleshooting time window extending over a given time period. The embodiment may include identifying a strict subset of the monitored KPIs based on portions of the respective timeseries spanning the given time period. The strict subset comprises abnormal KPIs (aKPIs) and potential explanatory KPIs (xKPIs). The embodiment may include obtaining a causal graph of vertices mapping KPIs of the strict subset by running a causality algorithm to evaluate weights of directed edges connecting the vertices and accordingly obtain one or more directed paths. The embodiment may include returning the obtained causal graph.

Abstract: A method of dynamically optimizing decision tree inference is provided. The method, which is performed at the computerized system, repeatedly executes one or more decision trees for inference purposes and repeatedly performs an optimization procedure according to two-phase cycles. Each cycle includes two alternating phases, i.e., a first phase followed by a second phase. The decision trees are executed based on a reference data structure, whereby attributes of nodes of the decision trees are repeatedly accessed from the reference data structure during the first phase of each of the cycles. First, the accessed attributes are monitored during the first phase of each cycle, which leads to update statistical characteristics of the nodes. Second, a substitute data structure is configured during the second phase of each cycle based on the updated statistical characteristics. Third, the reference data structure is updated in accordance with the substitute data structure.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Abstract: A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Abstract: The invention is directed to characterizing a computerized system. Access key performance indicators (KPIs), for the computerized system. Each of the KPIs is a timeseries of KPI values and is categorized into one of n types. KPI values are channeled through n buffer channels. Each buffer channel buffers KPI values of one of n types. Finally, reconstructions errors are obtained by feeding initial KPI values to n respective input channels of a cognitive model, implemented as an autoencoder by a trained neural network including an encoder and a decoder. Encoder has temporal convolutional layer blocks connected by each input channel. Decoder has deconvolution layer blocks connected by encoder. Initial KPI values are independently processed in n input channels, then compressed by encoder, prior to being reconstructed by decoder. Reconstruction errors are obtained by comparing reconstructed KPI values with initial KPI values. Computerized system is characterized based on reconstruction errors obtained.

Abstract: The invention is notably directed to a computer-implemented method, which aims at jointly identifying an optimal source of computerized resources and optimizing a configuration of the computerized resources. The method comprises configuring a Best-Arm Identification algorithm, in order to (i) associate arms of the algorithm with respective sources of computerized resources and (ii) connect the arms to one or more optimizers. Each of the optimizers is designed to optimize a configuration of such computerized resources. Next, the method iteratively executes the Best-Arm Identification algorithm to progressively eliminate the sources, with a view to eventually identifying one of the sources as an optimal source with an optimized configuration. Several iterations are accordingly performed. During each iteration, each of the arms is pulled and the rewards earned by pulling the arms are computed. Pulling each arm causes to optimize a configuration of computerized resources of a respectively associated source.

Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Abstract: Accessing a value M identifying M top levels of one or more N decision trees, wherein 1 ? M < Min(L1, ...., LN) and wherein a M top levels defines top nodes for each of the N decision trees, and wherein for each decision tree Ti of the N decision trees. Identifying one or more subtrees subtended by respective subsets of remaining nodes of each decision tree Ti, a remaining nodes including all of the nodes of said each decision tree Ti but its top nodes. Processing each of the K input records through a top nodes of said each decision tree Ti to associate each of the K input records with a single, respective one of the subtrees of each decision tree Ti, wherein K × N associations are obtained in total for the N decision trees and the K input records.

Abstract: A tensor representation of a machine learning inferences to be performed is built by forming complementary tensor subsets that respectively correspond to complementary subsets of one or more leaf nodes of one or more decision trees based on statistics of the one or more leaf nodes of the one or more decision trees and data capturing attributes of one or more split nodes of the one or more decision trees and the one or more leaf nodes of the decision trees. The complementary tensor subsets are ranked such that a first tensor subset and a second tensor subset of the complementary tensor subsets correspond to a first leaf node subset and a second leaf node subset of the complementary subsets of the one or more leaf nodes.

Abstract: A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.