Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130), possibly dielectric, coated with a conductive material (144) which provides one or more conductive lines. In some embodiments, the conductive material covers a part, but not all, of the polymer member. In some embodiments, multiple conductive lines are formed on the polymer member. In some embodiments, the polymer member is conductive. Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Abstract: In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract: A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure.

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.

Abstract: A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract: A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract: Apparatus relating generally to a back-end-of-line (“BEOL”) stack. In this apparatus, the BEOL stack is configured to electrically couple at least one first electrical component to at least one second electrical component. First contacts are provided on a first side of the BEOL stack with a first pitch for providing a bondable surface for connection to the at least one first electrical component. Second contacts are provided on a second side of the BEOL stack with a second pitch for providing another bondable surface for connection to the at least one second electrical component. The second pitch may be larger than the first pitch.

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.