Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287184
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20160049417
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9184175
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20150170979
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20140264532
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 8699267
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. In one embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 15, 2014
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Publication number: 20130270502
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. In one embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Application
    Filed: June 5, 2013
    Publication date: October 17, 2013
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 8462545
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: June 11, 2013
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 8440535
    Abstract: A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 14, 2013
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20120256154
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Application
    Filed: June 19, 2012
    Publication date: October 11, 2012
    Inventors: CHARLES H. DENNISON, STEPHEN J. HUDGENS
  • Publication number: 20120220099
    Abstract: A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 30, 2012
    Inventor: Charles H. Dennison
  • Patent number: 8223538
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: July 17, 2012
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 8188454
    Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 29, 2012
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20120081956
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 5, 2012
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 8097514
    Abstract: A support material for a semiconductor device is processed. An opening having a width is etched into the support material for the semiconductor device using a first etch mask. A portion of the opening is etched using a second etch mask without alignment thereof to the width of the opening.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 17, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 8098519
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 17, 2012
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 8067761
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: November 29, 2011
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 8030734
    Abstract: A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 4, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Charles H. Dennison, George A. Gordon, John Peters
  • Patent number: 7917692
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: March 29, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
  • Publication number: 20110031460
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Application
    Filed: October 20, 2010
    Publication date: February 10, 2011
    Inventor: Charles H. Dennison