Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7355203
    Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7348268
    Abstract: A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Patent number: 7350018
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: March 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
  • Patent number: 7323707
    Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Patent number: 7314776
    Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 1, 2008
    Assignee: Ovonyx, Inc.
    Inventors: Brian G. Johnson, Charles H. Dennison
  • Patent number: 7315082
    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: January 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Trung T. Doan
  • Publication number: 20070279974
    Abstract: Rather than depositing a heater material into a pore, a heater material may be first blanket deposited over a select device. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between adjacent stacks that form separate cells may be filled with an insulator. After removing the mask material, a pore is then formed in the insulator over the heater. This may then be filled with chalcogenide to form a phase change memory.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventors: Charles H. Dennison, John M. Peters
  • Patent number: 7291917
    Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: November 6, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7282440
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 7282447
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Charles H Dennison, Trung T. Doan
  • Patent number: 7276448
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Charles H Dennison, Trung T. Doan
  • Patent number: 7274049
    Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7155561
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison
  • Patent number: 7119397
    Abstract: A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
  • Patent number: 7105408
    Abstract: A select device may have its threshold current reduced relative to the threshold current of a phase change memory element by providing within the select device a breakdown layer. Because the breakdown layer forms a breakdown filament along its length, the relative area between layers may be reduced, reducing the threshold current of the select device relative to that of the memory element. In addition, a stack may be formed with the select device over the memory element. The select device may be arranged so that the position of the breakdown filament may be moved inwardly relative to the etched edge to also reduce leakage current. In one embodiment, sidewall spacers may be formed on a portion of the select device.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Patent number: 7064036
    Abstract: Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: June 20, 2006
    Assignee: Micron Technology, Inc.
    Inventors: John K. Zahurak, Brent Keeth, Charles H. Dennison
  • Patent number: 6990017
    Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 24, 2006
    Assignee: Intel Corporation
    Inventors: Ward D. Parkinson, Charles H. Dennison, Stephen Hudgens
  • Patent number: 6967146
    Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: David L. Dickerson, Richard H. Lane, Charles H. Dennison, Kunal R. Parekh, Mark Fischer, John K. Zahurak
  • Patent number: 6948027
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: September 20, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
  • Patent number: RE39665
    Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 29, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Michael A. Walker