Abstract: A structured-core laminate panel can be made in an efficient, structurally sound manner, even without the use of adhesives (film or liquid forms) using materials with different melt or glass transition temperatures. In one implementation, a manufacturer positions one or more resin substrates about a structured core member, which comprises a relatively high melt or glass transition temperature compared with that of the one or more resin substrates. The manufacturer heats the assembly to at least the glass transition temperature of the resin substrates, but not to the melt or glass transition temperature of the structured core member. This allows the one or more resin substrates to melt and bond (mechanically, chemically, or both) to the structured core member on one side (or inner surface), while maintaining a substantially planar or original conformation on an opposing side (or outer surface).

Abstract: A method for manufacturing the biopolymer panel may include positioning a plurality of biopolymer sheets adjacent to one another, and subjecting them to a laminating temperature that exceeds the glass-transition temperature of the sheets for a time period sufficient to achieve lamination. The laminate panel is then quenched at a quenching temperature that is below the glass-transition temperature. The time period during lamination, as well as any “rest” period between lamination and quenching, is sufficiently short so as to prevent clouding or hazing as a result of crystallization of the biopolymer resin materials. In addition, the panel exhibits sufficient flame retardency to meet applicable building codes, exhibits sufficient impact resistance for use as a decorative or structural panel building material, and exhibits no substantial thermally induced degradation as a result of subjection to the laminating temperature. The panels may be used as decorative or structural building materials.

Abstract: Implementations of the present invention relate to for incorporating virgin or recycled thermoplastic resin materials into architectural thermoplastic panels that have ordered and reproducible geometric patterns. More specifically, at least one implementation provides a method for fusing thermoplastic elongated members, such as circular rods and rectangular bars, sourced from recycled thermoplastic resin to form the architectural thermoplastic panels.

Abstract: A structured-core laminate panel can be made in an efficient, structurally sound manner without the use of adhesives (film or liquid forms) using materials with different melt or glass transition temperatures. In one implementation, a manufacturer positions one or more resin substrates about a structured core, which comprises a relatively high melt or glass transition temperature compared with that of the one or more resin substrates. The manufacturer heats the assembly to at least the glass transition temperature of the resin substrates, but not to the melt or glass transition temperature of the structured core. This allows the one or more resin substrates to melt and bond (mechanically, chemically, or both) to the structured core on one side (or inner surface), while maintaining a substantially planar or original conformation on an opposing side (or outer surface).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly.

Abstract: Implementations of the present invention relate to systems, methods, and apparatus for manufacturing aesthetically pleasing architectural resin panels having a thick three-dimensional interlayer. In particular, at least one implementation includes a layup assembly that includes a decorative interlayer, positioned between resin sheets, that decorative interlayer comprising one or more three-dimensional decorative objects and one or more resin blocks. At least one implementation also includes a single-step lamination or pressing process that uses a combination of heat and pressure to melt the resin sheets and the resin blocks together, forming a decorative resin panel which includes the three-dimensional objects.

Abstract: A structured-core laminate panel can be made in an efficient, structurally sound manner without the use of adhesives (film or liquid forms) using materials with different melt or glass transition temperatures. In one implementation, a manufacturer positions one or more resin substrates about a structured core, which comprises a relatively high melt or glass transition temperature compared with that of the one or more resin substrates. The manufacturer heats the assembly to at least the glass transition temperature of the resin substrates, but not to the melt or glass transition temperature of the structured core. This allows the one or more resin substrates to melt and bond (mechanically, chemically, or both) to the structured core on one side (or inner surface), while maintaining a substantially planar or original conformation on an opposing side (or outer surface).

Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly.

Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The instructions executed by the computers (12) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise required an interrupt of an otherwise active computer. For example, one computer (12f) can be used to monitor an input/output port of the computer array (10).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (48). The micro-loop (100) in combination with the ability of the computers (12) to send instruction words (48) to a neighboring computer (12) provides a powerful tool for allowing a computer (12) to utilize the resources of a neighboring computer (12).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Abstract: A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).

Abstract: A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die.

Abstract: A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to save and retrieve data and/or instructions from memory. A stack register selector contains a plurality of stack registers and a plurality of shift registers, which are interconnected. The stack registers are selected by the shift registers in such a way that the stack registers operate in a circular repeating pattern, which prevents overflow and underflow of stacks.