Abstract: A ROM patching facility is disclosed which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The disclosed equipment repatches one or more times a ROM address that has already been patched. Upon the detection of each such address, the program information associated with the most recent implemented patch is returned to the system. The disclosed equipment comprises a plurality of PROM decoders for detecting ROM addresses that are to be patched and for generating output signals representing each patched address, encoders for receiving the decoder output signals and for encoding each such signal into binary address information, and auxiliary memories controlled by the encoder address information for providing valid program information to the system upon each detection of a patched ROM address.

Abstract: A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to detect the receipt of each address word representing a defective ROM locaton. Upon each detection of a defective address, the decoder temporarily inhibits the output of the ROM and causes a small auxiliary memory to output valid program information as a substitute for that in the defective ROM location. A counter is used as a supplemental addressing source for both the decoder and the auxiliary memory. This increases the patching capability by subdividing the decoder and the auxiliary memory into 2.sup.n segments where n is the number of bits supplied by the counter.

Abstract: A read only memory (ROM) patching arrangement is disclosed for providing valid output information whenever defective ROM word locations containing invalid information are addressed. The disclosed arrangement, which includes a decoder comprising a plurality of small capacity PROMs, detects the receipt of each address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary memory to output valid information as a substitute for that in the defective ROM location. The patching capability of the auxiliary memory and the decoder PROMs is increased by extending n bits of each ROM address word to n inputs of the auxiliary memory as well as to n inputs of each decoder PROM. The remaining inputs of the decoder PROMs, taken collectively, each receive a different one of the remaining bits of each ROM address.