Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

Abstract: Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views. Random nets are generated based on the views, view inputs, and pruning thresholds. Certain views are then selected as dominant based on a comparison of the output slews different nets and views. Subsequent analysis is then performed and used to update the design without using the pruned views (e.g., using the selected dominant views).

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.

Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.

Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

Abstract: A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure.

Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Abstract: In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin.

Abstract: A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.