Patents by Inventor Charles Jay Alpert

Charles Jay Alpert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10402522
    Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Thomas Andrew Newton, William Robert Reece
  • Patent number: 10402533
    Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: William Robert Reece, Yi-Xiao Ding, Thomas Andrew Newton, Charles Jay Alpert, Zhuo Li
  • Patent number: 10380287
    Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dirk Meyer, Zhuo Li, Charles Jay Alpert
  • Patent number: 10354040
    Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amin Farshidi, Thomas Andrew Newton, Zhuo Li, Charles Jay Alpert
  • Patent number: 10318693
    Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Zhuo Li, Charles Jay Alpert, William Robert Reece, Thomas Andrew Newton
  • Patent number: 10289797
    Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Wen-Hao Liu, Thomas Andrew Newton
  • Patent number: 10289775
    Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian Wilson, Charles Jay Alpert, Zhuo Li
  • Patent number: 10289795
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Charles Jay Alpert, Zhuo Li
  • Patent number: 10282506
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dirk Meyer, Zhuo Li, Charles Jay Alpert
  • Patent number: 10198551
    Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amin Farshidi, Zhuo Li, Charles Jay Alpert, William Robert Reece
  • Patent number: 10102328
    Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 16, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Zhuo Li, Charles Jay Alpert, Mehmet Can Yildiz
  • Patent number: 9785738
    Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Charles Jay Alpert, Zhuo Li, Wing Kai Chow, Wen-Hao Liu, Derong Liu
  • Patent number: 9106560
    Abstract: A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 9038009
    Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
  • Patent number: 9026976
    Abstract: In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 8930873
    Abstract: A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Gi-Joon Nam, Sven Peyer, Sourav Saha, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 8897998
    Abstract: A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 8892344
    Abstract: A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 8881089
    Abstract: A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions (“selected solution”) for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Glenn R. Bee, Zhuo Li, Tuhin Mahmud, Stephen T. Quay, Lakshmi N. Reddy, Chin Ngai Sze, Yaoguang Wei
  • Patent number: 8831875
    Abstract: A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Zhuo Li, Chin Ngai Sze, Yaoguang Wei