Abstract: Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Abstract: Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.

Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.

Abstract: Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the flux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

Abstract: A method for reducing the dynamic range required of an automatic gain control (AGC) circuit in a remote transceiver in 2-way communication between local and remote transceivers. By repeatedly transmitting a signal with successively increasing power from one transceiver until a response is received from the other transceiver, the dynamic range and hence complexity of the receiving circuit may be greatly reduced. The operating power of the remote transmitter can then be adjusted according to the level used by the local transmitter, thereby promoting the efficent use of the remote's power supply.

Abstract: The present invention provides for a method and an apparatus for routing electrical signals. The method includes accessing a plurality of electrical circuits. The apparatus includes a supervisory circuit capable of delivering two access signals from a group of first, second, third, and fourth access signals, wherein the supervisory circuit is capable of delivering one of the first and third access signals, and one of the second and fourth access signals. A plurality of electrical circuits is organized into first and second rows. A first portion of the plurality of electrical circuits in the first and second rows, is coupled to a first access signal line. A second portion of the plurality of electrical circuits in the first and second rows is coupled to a second access signal line. The first and second portions of the plurality of electrical circuits in said first row are coupled to a third access signal.

Abstract: A method and system that uses an anticipatory signal to pre-adjust the output of the power supply to compensate for an upcoming load change, thereby minimizing the voltage deviation at the load. A control circuit, such as a processor, controlling the system generates an anticipatory signal indicating an upcoming change in the load that is input to the power supply. The power supply, in response to the signal from the processor, adjusts the output of the power supply accordingly to compensate for the upcoming load change. When the system performs the operation that results in the load change, the power supply output has already been adjusted accordingly and the deviation of the load voltage caused by the change in the load is minimized.

Abstract: One or more interrogating commander stations and an unknown plurality of responding responder stations coordinate use of a common communication medium. Each commander station and each responder station is equipped to broadcast messages and to check for error in received messages. When more than one station attempts to broadcast simultaneously, an erroneous message is received and communication is interrupted. To establish uninterrupted communication, a commander station broadcasts a command causing each responder station of a potentially large first number of responder stations to each select a random number from a known range and retain it as its arbitration number. After receipt of such a command, each addressed responder station transmits a response message containing its arbitration number. Zero, one, or several responses may occur simultaneously.

Abstract: A method for reducing the dynamic range required of a receiver circuit in a remote transceiver in 2-way communication between local and remote transceivers. By repeatedly transmitting a signal with successively increasing power from one transceiver until a response is received from the other transceiver, the dynamic range and hence complexity of the receiving circuit may be greatly reduced. The operating power of the remote transmitter can then be adjusted according to the level used by the local transmitter, thereby promoting the efficent use of the remote's power supply.

Abstract: A protocol is used to coordinate the use of a common communication medium by one or more interrogating commander stations and an unknown plurality of responding responder stations. Each commander station and each responder station is equipped to broadcast messages and to check for error in received messages. When more than one station attempts to broadcast simultaneously, an erroneous message is received and communication is interrupted. To establish uninterrupted communication, a commander station broadcasts a command causing each responder station of a potentially large first number of responder stations to each select a random number from a known range and retain it as its arbitration number. After receipt of such a command, each addressed responder station transmits a response message containing its arbitration number. Zero, one, or several responses may occur simultaneously.