Patents by Inventor Charles L. Ingalls

Charles L. Ingalls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272958
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11062753
    Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner
  • Publication number: 20210183428
    Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11031400
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210143142
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Patent number: 10998027
    Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls, Tae H. Kim
  • Publication number: 20210125661
    Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210090625
    Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Inventors: Charles L. Ingalls, Tae H. Kim
  • Publication number: 20210090636
    Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Christopher J. Kawamura, Charles L. Ingalls, Tae H. Kim
  • Patent number: 10957382
    Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10957681
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Publication number: 20210074714
    Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.
    Type: Application
    Filed: October 28, 2020
    Publication date: March 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10943642
    Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210066272
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Patent number: 10930653
    Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Michael Amiel Shore, Charles L. Ingalls, Steve V. Cole
  • Patent number: 10916548
    Abstract: An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10916295
    Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10910049
    Abstract: A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-up circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Tae H. Kim
  • Patent number: 10910038
    Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Charles L. Ingalls, Tae H. Kim
  • Publication number: 20210028176
    Abstract: An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Scott J. Derner, Charles L. Ingalls