Abstract: An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).

Abstract: A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.

Abstract: A radio frequency transceiver (102), including a transmitter (104), a duplexer (108) and a direct-conversion receiver (106) including a mixer (140 and 141). An IIP2 calibration system (170), coupled to the transceiver, includes an IIP2 coefficient estimator (172) for calculating an estimate of second-order distortion intermodulation distortion, and an IIP2 controller (174) for adjusting an IIP2 tuning port of the mixer in the receiver to minimize second-order distortion intermodulation distortion in the receiver that may be caused by the receiver receiving a transmit RF signal leaking through the duplexer.

Abstract: A radio frequency transceiver (102), including a transmitter (104), a duplexer (108) and a direct-conversion receiver (106) including a mixer (140 and 141). An IIP2 calibration system (170), coupled to the transceiver, includes an IIP2 coefficient estimator (172) for calculating an estimate of second-order distortion intermodulation distortion, and an IIP2 controller (174) for adjusting an IIP2 tuning port of the mixer in the receiver to minimize second-order distortion intermodulation distortion in the receiver that may be caused by the receiver receiving a transmit RF signal leaking through the duplexer.

Abstract: A radio frequency transceiver (102), including a transmitter (104), a duplexer (108) and a direct-conversion receiver (106) including a mixer (140 and 141). An IIP2 calibration system (170), coupled to the transceiver, includes an IIP2 coefficient estimator (172) for calculating an estimate of second-order distortion intermodulation distortion, and an IIP2 controller (174) for adjusting an IIP2 tuning port of the mixer in the receiver to minimize second-order distortion intermodulation distortion in the receiver that may be caused by the receiver receiving a transmit RF signal leaking through the duplexer.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.

Abstract: At least one adjustable gain analog amplifier (120, 124 and 128) in an analog line-up (102) amplifies by a gain an analog signal at an input of the analog line-up (102). The at least one adjustable gain analog amplifier (120, 124 and 128) is operable at one or more gains. At least one digital estimation device (134, 140 and 146) receives signal via an output (108) of the analog line-up (10) and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier (120, 124 and 128) in the analog line-up (102). An AGC controller (152) monitors the digital signal estimate. The AGC controller (152) adjusts the gain of the at least one analog amplifier (120, 124 and 128). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.

Abstract: A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.

Abstract: A radio frequency transceiver (102), including a transmitter (104), a duplexer (108) and a direct-conversion receiver (106) including a mixer (140 and 141). An IIP2 calibration system (170), coupled to the transceiver, includes an IIP2 coefficient estimator (172) for calculating an estimate of second-order distortion intermodulation distortion, and an IIP2 controller (174) for adjusting an IIP2 tuning port of the mixer in the receiver to minimize second-order distortion intermodulation distortion in the receiver that may be caused by the receiver receiving a transmit RF signal leaking through the duplexer.

Abstract: An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).

Abstract: At least one adjustable gain analog amplifier (120, 124 and 128) in an analog line-up (102) amplifies by a gain an analog signal at an input of the analog line-up (102). The at least one adjustable gain analog amplifier (120, 124 and 128) is operable at one or more gains. At least one digital estimation device (134, 140 and 146) receives signal via an output (108) of the analog line-up (10) and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier (120, 124 and 128) in the analog line-up (102). An AGC controller (152) monitors the digital signal estimate. The AGC controller (152) adjusts the gain of the at least one analog amplifier (120, 124 and 128). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.

Abstract: A generator (304) generates first and second training signals (320, 318) that originate within a wireless communication device (FIG. 3) instead of being received from a source outside the device. A receive portion (212, 214, 216) of the device processes the first training signal to derive a processed training signal. An adaptive equalizer (310) equalizes the processed training signal to derive an equalized training signal. A processor (312) compares the equalized training signal and the second training signal using an adaptive algorithm to derive coefficients for the adaptive equalizer to compensate for variations in the receive portion, and adjusts the adaptive equalizer in accordance with the coefficients to derive a compensated output signal.

Abstract: A signal processing apparatus preferably suitable for implementation as an integrated circuit, that is arranged and constructed to be shared for processing a plurality of signals without interference between the signals and method thereof, the signal processing apparatus comprising: an input multiplexer for sequentially selecting from among the plurality of signals to provide a sequence of selected signals; a processing unit for processing the sequence of selected signals to provide a sequence of processed signals, the processing unit having an input coupled to the input multiplexer and a delay stage including a plurality of series coupled delay elements with one delay element corresponding to each of the plurality of signals; and an output de-multiplexer for sequentially selecting from the sequence of processed signals to provide a plurality of processed signals corresponding one to one with the plurality of signals.

Abstract: A signal processing apparatus 200, 800, preferably suitable for implementation as an integrated circuit, that is arranged and constructed to be shared for processing a plurality of signals without interference between the signals and method 1200 thereof, the signal processing apparatus comprising: an input multiplexer 203, 803 for sequentially selecting from among the plurality of signals to provide a sequence of selected signals; a processing unit 205, 805 for processing the sequence of selected signals to provide a sequence of processed signals, the processing unit having an input coupled to the input multiplexer and a delay stage 319, 1111 including a plurality of series coupled delay elements with one delay element corresponding to each of the plurality of signals; and an output de-multiplexer 209, 807 for sequentially selecting from the sequence of processed signals to provide a plurality of processed signals corresponding one to one with the plurality of signals.

Abstract: A generator (304) generates first and second training signals (320, 318) that originate within a wireless communication device (FIG. 3) instead of being received from a source outside the device. A receive portion (212, 214, 216) of the device processes the first training signal to derive a processed training signal. An adaptive equalizer (310) equalizes the processed training signal to derive an equalized training signal. A processor (312) compares the equalized training signal and the second training signal using an adaptive algorithm to derive coefficients for the adaptive equalizer to compensate for variations in the receive portion, and adjusts the adaptive equalizer in accordance with the coefficients to derive a compensated output signal.

Abstract: A null-pilot symbol assisted fast automatic frequency control (AFC) system for coherent demodulation of carrier phase modulation (CPM) includes (209) a pilot clock driven phase differentiator (252,253,255) for operating once every pilot clock cycle to determine the difference between the phase at a current pilot symbol location and the phase at a previous pilot symbol location. A frequency offset selector (256) is then used for choosing the most likely frequency offset from amongst a set of all frequency offsets that give rise to the same phase difference.

Abstract: A null-pilot symbol assisted fast automatic frequency control (AFC) system for coherent demodulation of carrier phase modulation (CPM) includes (209) a pilot clock driven phase differentiator (252,253,255) for operating once every pilot clock cycle to determine the difference between the phase at a current pilot symbol location and the phase at a previous pilot symbol location. A frequency offset selector (256) is then used for choosing the most likely frequency offset from amongst a set of all frequency offsets that give rise to the same phase difference.