Abstract: An apparatus having improved safety and performance characteristics for the removal of a coating from a tubular member, and particularly adapted for the removal of a concrete weight coat from submerged oil pipelines, comprising a generally C-shaped rigid frame member which is maintained in proper alignment by contact with the upper coated surface, is provided with a plurality of opposed, inwardly directed driven crusher blades located proximate the ends of the frame member and controlled driving means which are adapted to move the crusher blades. The method comprises positioning the apparatus on the coated pipeline, crushing the coating, raising the entire apparatus to free the fractured coating from the pipeline, retracting the crusher blades, and moving the apparatus to a new position on the pipeline.

Abstract: A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.

Abstract: An integrated circuit chip in which clock pulses are distributed to a plurality of circuits includes a pattern of trimmable elements such as capacitors or transistors. The capacitors or transistors are trimmed during manufacture in order, for example, to adjust clock skew.

Abstract: A complementary MOS static EXCLUSIVE OR gate is formed by a PMOS logic network having a pair of cross-coupled PMOS transistors and an NMOS logic network having two parallel branches, each of the branches containing a separate pair of NMOS transistors connected in series.

Abstract: A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.

Abstract: A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals.