Patents by Inventor Charles Parkhurst

Charles Parkhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10513332
    Abstract: An aircraft includes a fuselage defining an aircraft attitude axis. The fuselage houses an engine fixed relative to the aircraft attitude axis. A rotor assembly is operatively connected to rotate back and forth relative to the aircraft attitude axis from a first position predominately for lift to a second position predominately for thrust. The rotor assembly includes a rotor that is operatively connected to be driven by the engine.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: December 24, 2019
    Assignee: SIKORSKY AIRCRAFT CORPORATION
    Inventors: Mark R. Alber, Jeffrey Parkhurst, Charles Gayagoy
  • Publication number: 20190222184
    Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventor: Charles PARKHURST
  • Patent number: 10284157
    Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Charles Parkhurst
  • Publication number: 20180181180
    Abstract: An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventor: Charles PARKHURST
  • Patent number: 9793707
    Abstract: Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter includes two current sense element/current clamp control loops. A fast response time control loop first engages and clamps a current spike. A precision control loop then engages to more accurately clamp the output current to a programmed set point. The precision clamping loop includes an inner loop to linearize the precision current sense element. The inner loop forces the drain-to-source voltage (VDS) of the precision sense element to track the VDS of the regulator pass element. A more precise clamping operation results. Overall speed is not sacrificed as the fast response time clamping loop operates in parallel to protect circuitry while the precision clamping loop engages.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hector Torres, Charles Parkhurst
  • Patent number: 9571051
    Abstract: An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles Parkhurst, Hector Torres
  • Publication number: 20150288337
    Abstract: An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 8, 2015
    Inventors: Charles PARKHURST, Hector TORRES
  • Patent number: 9018923
    Abstract: Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the beginning of a static bias startup period shortly after power-on. The dynamically biased apparatus is then gradually enabled in a static bias mode of operation during the static bias startup period. Following the end of the static bias startup period, operation of the dynamically biased apparatus in a dynamic transconductance mode is gradually enabled during a dynamic bias startup period. Such startup sequence operates to prevent damaging in-rush currents in a system employing the dynamically biased apparatus in a feedback control loop.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: April 28, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Patent number: 9000844
    Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Charles Parkhurst
  • Publication number: 20140355161
    Abstract: Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter includes two current sense element/current clamp control loops. A fast response time control loop first engages and clamps a current spike. A precision control loop then engages to more accurately clamp the output current to a programmed set point. The precision clamping loop includes an inner loop to linearize the precision current sense element. The inner loop forces the drain-to-source voltage (VDS) of the precision sense element to track the VDS of the regulator pass element. A more precise clamping operation results. Overall speed is not sacrificed as the fast response time clamping loop operates in parallel to protect circuitry while the precision clamping loop engages.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Hector Torres, Charles Parkhurst
  • Patent number: 8896323
    Abstract: Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: November 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Publication number: 20130187620
    Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Inventor: Charles Parkhurst
  • Publication number: 20130141059
    Abstract: Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the beginning of a static bias startup period shortly after power-on. The dynamically biased apparatus is then gradually enabled in a static bias mode of operation during the static bias startup period. Following the end of the static bias startup period, operation of the dynamically biased apparatus in a dynamic transconductance mode is gradually enabled during a dynamic bias startup period. Such startup sequence operates to prevent damaging in-rush currents in a system employing the dynamically biased apparatus in a feedback control loop.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 6, 2013
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Patent number: 8436682
    Abstract: Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 7, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Publication number: 20130099863
    Abstract: Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Publication number: 20130099796
    Abstract: Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Patent number: 8390327
    Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Publication number: 20130043903
    Abstract: A system and method for radiation-tolerant level shifting are disclosed. In some embodiments, an integrated circuit may include a plurality of level shifters, where each of the plurality of level shifters configured receive a same logic level in a first voltage domain and to output candidate logic levels in a second voltage domain, and where at least one of the candidate logic levels subject to being different from another one of the candidate logic levels. The integrated circuit may also include a voting circuit coupled to the plurality of level shifters, where the voting circuit is configured to evaluate the candidate logic levels and output a selected logic level based, at least in part, upon the evaluation.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charles Parkhurst, Mark Hamlyn
  • Patent number: 8228108
    Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: July 24, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hector Torres, Charles Parkhurst
  • Publication number: 20110095798
    Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective ones of two reference voltages.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 28, 2011
    Inventors: Hector Torres, Charles Parkhurst