Patents by Inventor Charles R. Johns
Charles R. Johns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9483424Abstract: Embodiments of the present disclosure use non-blocking writes (NBWs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using NBWs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may indicate that a TLP includes an NBW. Based on the indication, the root complex may send the NBWs on a dedicated NBW channel such that the NBW is not blocked by normal memory writes.Type: GrantFiled: December 4, 2015Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles R. Johns, Eric N. Lais, Jeffrey A. Stuecheli
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Publication number: 20160217101Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.Type: ApplicationFiled: April 27, 2015Publication date: July 28, 2016Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
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Publication number: 20160217096Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.Type: ApplicationFiled: January 27, 2015Publication date: July 28, 2016Inventors: Charles R. Johns, Andrew T. Koch, Gregory M. Nordstrom
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Patent number: 9390015Abstract: A method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially-requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.Type: GrantFiled: March 16, 2006Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventor: Charles R. Johns
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Patent number: 9053069Abstract: A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.Type: GrantFiled: August 23, 2012Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Daniel A. Brokenshire, Charles R. Johns, Mark R. Nutter, Barry L. Minor
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Patent number: 9009420Abstract: A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.Type: GrantFiled: March 22, 2012Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventor: Charles R. Johns
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Patent number: 8918553Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.Type: GrantFiled: June 5, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Brian K. Flachs, Harm P. Hofstee, Charles R. Johns, Matthew E. King, John S. Liberty, Brad W. Michael
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Patent number: 8734254Abstract: A mechanism is provided for generating event notifications for offline characters from within a persistent world online game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent composes an event notification message and sends the message to the offline player. Event notification messages may include images, voice (text-to-speech), sound, or video. Offline players may receive event notifications at various messaging clients, such as personal computers and wireless telephones. A notification server may transmit the event notifications via existing communications channels, such as electronic mail, facsimile, instant messaging, text messaging, and voice communications.Type: GrantFiled: April 25, 2006Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Maximino Aguilar, Jr., Charles R. Johns, Mark R. Nutter
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Patent number: 8627043Abstract: Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.Type: GrantFiled: March 26, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter
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Patent number: 8627042Abstract: Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.Type: GrantFiled: December 30, 2009Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter
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Patent number: 8583905Abstract: Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.Type: GrantFiled: March 30, 2012Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter
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Patent number: 8572359Abstract: Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.Type: GrantFiled: December 30, 2009Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter
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Patent number: 8520740Abstract: Mechanisms for performing decoding of context-adaptive binary arithmetic coding (CABAC) encoded data. The mechanisms receive, in a first single instruction multiple data (SIMD) vector register of the data processing system, CABAC encoded data of a bit stream. The CABAC encoded data includes a value to be decoded and bit stream state information. The mechanisms receive, in a second SIMD vector register of the data processing system, CABAC decoder context information. The mechanisms process the value, the bit stream state information, and the CABAC decoder context information in a non-recursive manner to generate a decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms store, in a third SIMD vector register, a result vector that combines the decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms use the decoded value to generate a video output on the data processing system.Type: GrantFiled: September 2, 2010Date of Patent: August 27, 2013Assignees: International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Brian Flachs, Charles R. Johns, Michael A. Kutner, Brad W. Michael, Naxin Wang
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Publication number: 20120317372Abstract: A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.Type: ApplicationFiled: August 23, 2012Publication date: December 13, 2012Applicant: International Business Machines CorporationInventors: Daniel A. Brokenshire, Charles R. Johns, Mark R. Nutter, Barry L. Minor
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Publication number: 20120284720Abstract: Apparatus and methods for hardware assisted scheduling of software tasks in a computer system are disclosed. For example, a computer system comprises a first pool for maintaining a set of executable software threads, a first scheduler, a second pool for maintaining a set of active software threads, and a second scheduler. The first scheduler assigns a subset of the set of executable software threads to the set of active software threads and the second scheduler dispatches one or more threads from the set of active software threads to a set of hardware threads for execution. In one embodiment, the first scheduler is implemented as part of the operating system of the computer system, and the second scheduler is implemented in hardware.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Applicant: International Business Machines CorporationInventors: Harold W. Cain, III, Hubertus Franke, Charles R. Johns, James A. Kahle, Hung Q. Le, Ravi Nair
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Publication number: 20120246354Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.Type: ApplicationFiled: June 5, 2012Publication date: September 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian K. Flachs, Harm P. Hofstee, Charles R. Johns, Matthew E. King, John S. Liberty, Brad W. Michael
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Patent number: 8275917Abstract: A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.Type: GrantFiled: May 27, 2008Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Daniel A. Brokenshire, Charles R. Johns, Mark R. Nutter, Barry L. Minor
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Patent number: 8265253Abstract: The present invention provides a method, system, and computer program product for displaying images of conference call participants. A method in accordance with an embodiment of the present invention includes receiving a call from a user to join a conference call, obtaining a phone number of the user, matching the phone number to a stored graphical representation, and distributing and displaying the matching graphical representation to a predetermined set of users. A voice identification/recognition process can also be used to match the user to a stored graphical representation.Type: GrantFiled: July 14, 2008Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventors: Bruce D. D'Amora, Charles R. Johns
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Publication number: 20120192167Abstract: Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter
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Publication number: 20120191953Abstract: Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexandre E. Eichenberger, Brian K. Flachs, Charles R. Johns, Mark R. Nutter