Patents by Inventor Charles Rimbert-Riviere

Charles Rimbert-Riviere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111049
    Abstract: A transportation system for semiconductor substrates includes a tray, lid and packaging bag. The tray includes a bottom and circumferential sidewalls. The tray has an opening on a top side and is configured to receive semiconductor substrates through the opening, the substrates being stacked onto each other in the tray in parallel to the tray bottom. The lid includes a cover plate and at least two arms extending from the plate. The arms are configured to be inserted into the tray between the tray sidewalls and the semiconductor substrates. The cover plate is configured to cover the tray opening when the lid is fully mounted to the tray. The packaging bag is configured to enclose the tray with the substrates stacked therein and lid arranged thereon, and to be evacuated of air and sealed such that the tray and lid arranged in the bag are vacuum sealed inside the bag.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 15, 2021
    Inventors: Michael Daginnus-Metzen, Evelin Palko, Benedikt Reuber, Charles Rimbert-Riviere
  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
  • Patent number: 10141199
    Abstract: A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder is provided. The insulating substrate includes a dielectric insulation carrier, a top side, and a bottom side opposite to the top side. The method includes selecting the insulating substrate based on a criterion which indicates that the insulating substrate, if it has the solidus temperature of the solder, has a positive unevenness. The insulating substrate is soldered on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion. The top side of the insulating substrate is populated with at least one semiconductor chip.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Charles Rimbert-Riviere, Jean-Laurent Deborde, Martin Haller, Nils Alexander Sanetra, Vasile Vartolomei
  • Patent number: 10074590
    Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20170062241
    Abstract: A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder is provided. The insulating substrate includes a dielectric insulation carrier, a top side, and a bottom side opposite to the top side. The method includes selecting the insulating substrate based on a criterion which indicates that the insulating substrate, if it has the solidus temperature of the solder, has a positive unevenness. The insulating substrate is soldered on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion. The top side of the insulating substrate is populated with at least one semiconductor chip.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 2, 2017
    Inventors: Charles Rimbert-Riviere, Jean-Laurent Deborde, Martin Haller, Nils Alexander Sanetra, Vasile Vartolomei