Patents by Inventor Charlotte DeWan Adams
Charlotte DeWan Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105769Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Shahab Siddiqui, Ruqiang Bao, Charlotte DeWan Adams, Curtis S. Durfee, Anthony I. Chou, Barry Paul Linder, Ravikumar Ramachandran, Dechao Guo
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Publication number: 20240079276Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Ruqiang Bao, Effendi Leobandung, Eric Miller, Charlotte DeWan Adams, Cornelius Brown Peethala, Liqiao Qin
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Patent number: 11888048Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Publication number: 20230029561Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: ApplicationFiled: October 15, 2022Publication date: February 2, 2023Inventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Patent number: 11515427Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: GrantFiled: June 15, 2020Date of Patent: November 29, 2022Assignee: International Business Machines CorporationInventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Publication number: 20220069104Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Inventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Patent number: 11211474Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: GrantFiled: January 14, 2020Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Publication number: 20210391473Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Publication number: 20210217873Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: ApplicationFiled: January 14, 2020Publication date: July 15, 2021Inventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Patent number: 8941177Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: GrantFiled: June 27, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Charlotte DeWan Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Publication number: 20140001575Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlotte DeWan Adams, Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui
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Patent number: 7741181Abstract: A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation.Type: GrantFiled: November 6, 2007Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Charlotte DeWan Adams, Naim Moumen, Ying Zhang
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Publication number: 20090114992Abstract: A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Inventors: Bruce B. Doris, Charlotte DeWan Adams, Naim Moumen, Ying Zhang
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Publication number: 20080272438Abstract: A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a liner without nitride portions. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have their threshold values set independently from one another.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Inventors: Bruce B. Doris, Charlotte DeWan Adams, Eduard Albert Cartier, Vijay Narayanan