Patents by Inventor Charvaka Duvvury

Charvaka Duvvury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10725098
    Abstract: A method for electrostatic discharge (ESD) testing and analysis includes performing, by an ESD testing device, ESD testing on pins of an integrated circuit (IC) device to generate pre-stress ESD test data for each of the pins and post-stress ESD test data for each of the pins, determining, current shifts according to first data points of voltage-current (IV) curves of the pre-stress ESD test data corresponding to the IC device pins and to second data points of IV curves of the post-stress ESD test data corresponding to the respective pins of the IC device, assigning, by the device, a test result classification for each of the pins according to a relationship between a test threshold and the current shift for the respective pin, and displaying, by a workstation, a visually coded map of the IC device indicating the test result classification for each of the pins.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 28, 2020
    Assignee: ESD IT2 LLC.
    Inventors: Charvaka Duvvury, Amjad Hussain, Svetlana Loshakov
  • Publication number: 20180100890
    Abstract: A method for electrostatic discharge (ESD) testing and analysis includes performing, by an ESD testing device, ESD testing on pins of an integrated circuit (IC) device to generate pre-stress ESD test data for each of the pins and post-stress ESD test data for each of the pins, determining, current shifts according to first data points of voltage-current (IV) curves of the pre-stress ESD test data corresponding to the IC device pins and to second data points of IV curves of the post-stress ESD test data corresponding to the respective pins of the IC device, assigning, by the device, a test result classification for each of the pins according to a relationship between a test threshold and the current shift for the respective pin, and displaying, by a workstation, a visually coded map of the IC device indicating the test result classification for each of the pins.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 12, 2018
    Inventors: Charvaka Duvvury, Amjad Hussain, Svetlana Loshakov
  • Patent number: 9269703
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 23, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • Publication number: 20140342515
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 20, 2014
    Inventors: Ponnarith POK, Kyle SCHULMEYER, Roger A. CLINE, Charvaka DUVVURY
  • Patent number: 8829618
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • Patent number: 8755158
    Abstract: An electronic system protected against an incoming energy pulse, comprising a semiconductor device (310a, 310b) connected in sequential order to a first impedance (320), a coupling noise filter (330) having an internal frequency-dependent second impedance (331), a third impedance (340), a transient voltage suppressor (350), a fourth impedance (360), and an entry port exposed to the incoming energy pulse (380).
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Stephane Bertonnaud
  • Publication number: 20130293992
    Abstract: An electronic system protected against an incoming energy pulse, comprising a semiconductor device (310a, 310b) connected in sequential order to a first impedance (320), a coupling noise filter (330) having an internal frequency-dependent second impedance (331), a third impedance (340), a transient voltage suppressor (350), a fourth impedance (360), and an entry port exposed to the incoming energy pulse (380).
    Type: Application
    Filed: December 6, 2012
    Publication date: November 7, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charvaka Duvvury, Stephane Bertonnaud
  • Patent number: 8530301
    Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Charvaka Duvvury
  • Publication number: 20120112286
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 10, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ponnarith Pok, Kyle Schulmeyer, Roger A. Cline, Charvaka Duvvury
  • Publication number: 20110266624
    Abstract: An ESD protection device for an I/O pad (401); the device comprising a MOS transistor (420) having at least one elongated source region (422) and at least one elongated drain region (421) in a substrate (400) of first conductivity, the length (420a) of the source and drain regions oriented in a direction, the source tied to ground potential (430); a diode having an area including at least one elongated anode region and at least one elongated cathode region in a well of opposite conductivity, the lengths of the anode and cathode regions oriented in the same direction as the transistor regions; the diode area and the well divided normal to the lengths of the anode and cathode regions into two portions (anode portions 411x, 411y, cathode portions 412x, 412y, length portions 410x, 410y, well portions 440x, 440y); and the anode portions connected to the I/O pad, and the cathode portions connected to the transistor drain.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 3, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charvaka DUVVURY, Yen-Yi LIN
  • Publication number: 20110194220
    Abstract: An electronic system including an assembly with a protection clamp for discharging a portion of the incoming pulse, the un-discharged residual pulse (132) including a spike voltage (150, 202) for a first time duration (151, 203) followed by a bulk voltage (160, 302) smaller than the spike voltage for a second time duration (161, 303) greater than the first time duration; an integrated circuit device coupled with the board, the device allowing a peak current (211) at the insulator breakdown voltage (213), and including a pin protection clamp allowing a threshold current (311) at a threshold voltage (313) during the second time duration; and an isolation impedance integrated with the system for weakening the residual pulse, the impedance being the greater of a first resistor (220), determined by dividing the voltage difference between spike and insulator breakdown voltage through the peak current, and a second resistor (320), determined by dividing the voltage difference between the bulk and threshold voltage t
    Type: Application
    Filed: February 2, 2011
    Publication date: August 11, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Charvaka DUVVURY, Steve E. MARUM
  • Publication number: 20110075306
    Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
    Type: Application
    Filed: December 9, 2010
    Publication date: March 31, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yves Leduc, Nathalie Messina, Charvaka Duvvury, Kurt P. Wachtler
  • Publication number: 20110063765
    Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p?layer (38) includes functional circuitry (24) formed on the p?layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p? layer (38), a p?doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p? layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p?region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 17, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gianluca Boselli, Charvaka Duvvury
  • Patent number: 7872841
    Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: January 18, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Yves Leduc, Nathalie Messina, Charvaka Duvvury, Kurt P. Wachtler
  • Patent number: 7864494
    Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: January 4, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Ming Hung, Charvaka Duvvury
  • Patent number: 7838924
    Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Charvaka Duvvury
  • Publication number: 20100226056
    Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
    Type: Application
    Filed: May 19, 2010
    Publication date: September 9, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chih-Ming Hung, Charvaka Duvvury
  • Patent number: 7746608
    Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Ming Hung, Charvaka Duvvury
  • Patent number: 7667243
    Abstract: A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: February 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Gianluca Boselli
  • Publication number: 20090267154
    Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Charvaka Duvvury