Patents by Inventor Charvaka Duvvury

Charvaka Duvvury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6624487
    Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, Charvaka Duvvury, Dan M. Mosher
  • Patent number: 6576959
    Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 10, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
  • Patent number: 6534833
    Abstract: The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry which comprises an integrated circuit having at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: March 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Michael D. Chaine, Puvvada Venugopal
  • Publication number: 20030048588
    Abstract: An output circuit for improved ESD protection (FIG. 2) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad 220 and Vdd power supply 240, the pull-up transistor located in a n-well 203 and having at least one gate 210, the gate connected to internal circuitry 230. A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well 203, whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate 251, this gate connected through a resistor 260 to the Vdd power supply 240. The n-well 203 connected to the Vdd power supply 240.
    Type: Application
    Filed: August 6, 2002
    Publication date: March 13, 2003
    Inventors: Charvaka Duvvury, Roger A. Cline
  • Patent number: 6493850
    Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 10, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C. S. Raghu, Gopalaro Kadamati
  • Patent number: 6469353
    Abstract: An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (104) which clamps to voltage at the pad (110) and dissipated the ESD current. The lateral npn (104) is the primary protection device for dissipating ESD current.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: E. Ajith Amerasekera, Charvaka Duvvury
  • Publication number: 20020152447
    Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.
    Type: Application
    Filed: February 16, 2001
    Publication date: October 17, 2002
    Inventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C.S. Raghu, Gopalaro Kadamati
  • Publication number: 20020145164
    Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
    Type: Application
    Filed: September 5, 2001
    Publication date: October 10, 2002
    Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
  • Patent number: 6462380
    Abstract: A structure is designed with a lightly doped substrate (316) having a first conductivity type and a face. A first lightly doped region (314) has a second conductivity type and is formed within the lightly doped substrate. A first heavily doped region (308) has the first conductivity type and is formed at the face and extends to a first depth within the first lightly doped region. A second heavily doped region (312) has the second conductivity type and is formed at the face abutting the first heavily doped region. The second heavily doped region extends to a second depth and is at least partly within the first lightly doped region. A first isolation region (304) is formed at the face, abutting at least one of the first and second heavily doped regions. The first isolation region extends to a third depth that is greater than either of the first and the second depths.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: October 8, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Michael D. Chaine
  • Patent number: 6365940
    Abstract: A tunable high voltage trigger silicon controlled rectifier (SCR) with a high holding voltage is disclosed. The source of a drain extended MOS serves as the remote cathode for the SCR, while the drain of the drain extended MOS serves to generate avalanche currents to trigger the SCR.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Roy Clifton Jones, III
  • Publication number: 20020030954
    Abstract: A semiconductor device is designed with a common supply voltage terminal (330). A plurality of standard cells (360-364), each having a plurality of leads (308,326) is connected to the common supply terminal. A plurality of connecting leads (322-324) corresponding to respective standard cells is coupled between at least two leads of the plurality of leads.
    Type: Application
    Filed: May 24, 2001
    Publication date: March 14, 2002
    Inventors: Charvaka Duvvury, Sridhar Ramaswamy
  • Patent number: 6249413
    Abstract: Protection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14).
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: June 19, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Charvaka Duvvury
  • Patent number: 6208493
    Abstract: A high-energy pulse protection device (10) protects an integrated circuit (28 and 30). The integrated circuit (28 and 30) is associated with an integrated circuit substrate region (64). The high-energy pulse protection device (10), has a protection circuit substrate region (74) that is disassociated from the integrated circuit substrate region (64). A primary protection circuit (40 and 42) is associated with the protection circuit substrate region (74) and has at least one connection (22) with the integrated circuit (28 and 30) for receiving and dissipating, through the at least one connection (22), a high-energy pulse. This protects the integrated circuit (28 and 30) from the high-energy pulse.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: March 27, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Charvaka Duvvury
  • Patent number: 6140683
    Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: October 31, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, David Douglas Briggs, Fernando David Carvajal
  • Patent number: 6137338
    Abstract: An input circuit is designed with an external terminal (104). A first input transistor (108) has a control gate coupled to the external terminal by a low resistance path (104). The first input transistor has a current path coupled to an output terminal (120). A first series transistor (110) has a control gate and a current path. The current path of the first series transistor is connected in series with the current path of the first input transistor. A primary clamp (102) is coupled to the external terminal.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Steven E. Marum, Charvaka Duvvury, Michael O. Chaine
  • Patent number: 6125021
    Abstract: An integrated circuit (10) with ESD protection is provided. The integrated circuit (10) includes a clamping device (28) connected to an input pad (12) of the integrated circuit and to ground (22). The clamping device (28) limits the peak voltage of an ESD pulse applied to the input pad (12) by conducting it to ground (22). A protection device (16) is connected to an input pad (12) of the integrated circuit (10) and to ground. The protection device (16) discharges the energy of the ESD pulse to ground. The protection device (16) is coordinated with the clamping device (28) such that the clamping device (28) turns on before the protection device (16).
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: September 26, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Steven E. Marum, Amitava Chatterjee
  • Patent number: 6078083
    Abstract: An ESD protection circuit for dual 3V/5V supply devices. ESD protection circuit 10 comprises a switching element 12 connected between a bond pad 14 and primary protection device 16. Primary protection device 16 comprises MOS circuitry designed for 3V operation that suffers from oxide reliability problems when 5V signals are applied directly. Switching element 12 separates the primary protection device 16 from 5V signals which may appear at bond pad 14.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: June 20, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Ekanayake Ajith Amerasekera, Charvaka Duvvury
  • Patent number: 6071768
    Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: June 6, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, David Douglas Briggs, Fernando David Carvajal
  • Patent number: 6064249
    Abstract: A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: May 16, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Fred Carvajal, David Briggs
  • Patent number: 6040968
    Abstract: A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: March 21, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, E. Ajith Amerasekera, Sridhar Ramaswamy