Patents by Inventor Chee Keong Chin

Chee Keong Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289395
    Abstract: A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Chee Keong Chin, Xin Lu
  • Patent number: 11177241
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Publication number: 20200381401
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Application
    Filed: March 10, 2020
    Publication date: December 3, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Publication number: 20200335481
    Abstract: A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 22, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Chee Keong Chin, Xin Lu
  • Patent number: 10483239
    Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Xiaofeng Di, Harjashan Singh, Gokul Kumar, Chee Keong Chin, Ming Xia Wu, Jian Bin Gu
  • Patent number: 10418334
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
  • Patent number: 10283485
    Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Xiaofeng Di, Chee Keong Chin, Kim Lee Bock, Mingxia Wu
  • Publication number: 20180337161
    Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.
    Type: Application
    Filed: June 8, 2017
    Publication date: November 22, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Junrong Yan, Xiaofeng Di, Chee Keong Chin, Kim Lee Bock, Mingxia Wu
  • Patent number: 10128218
    Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 13, 2018
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
  • Publication number: 20180190621
    Abstract: A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Junrong Yan, Xiaofeng Di, Harjashan Singh, Gokul Kumar, Chee Keong Chin, Ming Xia Wu, Jian Bin Gu
  • Publication number: 20180174983
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Application
    Filed: June 22, 2017
    Publication date: June 21, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
  • Publication number: 20180175006
    Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.
    Type: Application
    Filed: June 22, 2017
    Publication date: June 21, 2018
    Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.
    Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
  • Patent number: 8946878
    Abstract: An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: February 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Chee Keong Chin, Jae Hak Yee, Yu Feng Feng, Frederick Cruz Santos
  • Patent number: 8901439
    Abstract: An integrated circuit package system includes a bottom lid, a base integrated circuit over the bottom lid, and a top lid with an integrated circuit window opening over the bottom lid.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Chee Keong Chin, Yu Feng Feng, Guo Qiang Shen
  • Patent number: 8541886
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 24, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventor: Chee Keong Chin
  • Patent number: 8288860
    Abstract: An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 16, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Chee Keong Chin, Yu Feng Feng, Wen Bin Qu
  • Patent number: 8242607
    Abstract: A method of manufacture of an integrated circuit package system comprises: providing a first integrated circuit die; attaching a second integrated circuit die over the first integrated circuit die and offset from the first integrated circuit die in substantially one dimension; forming an interdie layer over the second integrated circuit die; attaching a third integrated circuit die over the interdie layer and substantially aligned to the second integrated circuit die; and attaching a fourth integrated circuit die over the third integrated circuit die and offset from the third integrated circuit die in substantially the same magnitude and substantially the opposite direction as the second integrated circuit die to the first integrated circuit die.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: August 14, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Chee Keong Chin
  • Patent number: 8138017
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a package substrate; mounting a first integrated circuit die, having through silicon vias, on the package substrate; coupling cylindrical studs to the package substrate adjacent to the first integrated circuit die; and mounting a second integrated circuit die, having through silicon vias, on the first integrated circuit die and the cylindrical studs for forming an electrical connection among the second integrated circuit die, the first integrated circuit die, the package substrate, or a combination thereof.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 20, 2012
    Assignee: Stats Chippac Ltd.
    Inventor: Chee Keong Chin
  • Patent number: 8037918
    Abstract: Pick-up heads and systems are especially useful for picking up, transporting, and placing semiconductor dies at bond sites on packaging substrates. Alternatively, the heads and systems are useful for performing these tasks with any of various other planar objects. An exemplary head includes a shank and a body. The body includes a compliant end portion contactable by the shank, and the end portion includes a face. The shank is movable relative to the end portion such that, whenever the shank is retracted, the face has a substantially planar contour, and whenever the shank is extended, the shank contacts and urges the end portion to provide the face with a convex contour. The end portion desirably defines at least one vacuum orifice connected to an evacuation device (e.g., a vacuum pump) that evacuates the vacuum orifice sufficiently to cause the planar object to adhere to the face.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Ya Ping Wang, Jian Ming Yang, Guo Qiang Shen, Chee Keong Chin
  • Publication number: 20110221072
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 15, 2011
    Inventor: Chee Keong Chin