Patents by Inventor Chee-Wee Liu

Chee-Wee Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked Vertically Isolated Mosfet Structure and Method of Forming the Same
    Publication number: 20200373334
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee Wee Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200328287
    Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.
    Type: Application
    Filed: April 13, 2019
    Publication date: October 15, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Pin-Shiang CHEN, Sheng-Ting FAN, Chee-Wee LIU
  • Semiconductor device and method for manufacturing the same
    Patent number: 10804180
    Abstract: A device includes a non-insulator structure, a first ILD layer, a first thermal via, and a first electrical via. The first ILD is over the non-insulator structure. The first thermal via is through the first ILD layer and in contact with the non-insulator structure. The first electrical via is through the first ILD layer and in contact with the non-insulator structure. The first thermal via and the first electrical via have different materials and the same height.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 13, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jhih-Yang Yan, Fang-Liang Lu, Chee-Wee Liu
  • Semiconductor device and formation thereof
    Patent number: 10777426
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Semiconductor device having boron-doped germanium tin epitaxy structure and method for forming the same
    Patent number: 10777663
    Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 15, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Fang-Liang Lu, Pin-Shiang Chen, Chee-Wee Liu
  • Method For Non-Resist Nanolithography
    Publication number: 20200287025
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • Stacked vertically isolated MOSFET structure and method of forming the same
    Patent number: 10748935
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: August 18, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee-Wee Liu
  • Semiconductor Device and Method
    Publication number: 20200243327
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Semiconductor device and manufacturing methods thereof
    Patent number: 10686072
    Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 16, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yu-Hung Liao, Samuel C. Pan, Sheng-Ting Fan, Min-Hung Lee, Chee-Wee Liu
  • Method for non-resist nanolithography
    Patent number: 10665696
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 26, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, National Taiwan University
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • NANOWIRE STACK GAA DEVICE WITH SELECTABLE NUMBERS OF CHANNEL STRIPS
    Publication number: 20200144367
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: May 7, 2020
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, CheeWee Chee-Wee Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200144368
    Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU
  • Semiconductor device and method
    Patent number: 10636651
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Semiconductor device and manufacturing method thereof
    Patent number: 10535737
    Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 14, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Stacked Vertically Isolated Mosfet Structure and Method of Forming the Same
    Publication number: 20200006389
    Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.
    Type: Application
    Filed: October 4, 2018
    Publication date: January 2, 2020
    Inventors: Yu-Shiang Huang, Hung-Yu Yeh, Wen Hung Huang, Chee-Wee Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190312132
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: I-Hsieh WONG, Samuel C. PAN, Chee-Wee LIU, Huang-Siang LAN, Chung-En TSAI, Fang-Liang LU
  • Multi-Channel Field Effect Transistors using 2D-Material
    Publication number: 20190252554
    Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee Wee Liu, Samuel C. Pan
  • Semiconductor device and manufacturing method thereof
    Patent number: 10332985
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 25, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20190164866
    Abstract: A device includes a non-insulator structure, a first ILD layer, a first thermal via, and a first electrical via. The first ILD is over the non-insulator structure. The first thermal via is through the first ILD layer and in contact with the non-insulator structure. The first electrical via is through the first ILD layer and in contact with the non-insulator structure. The first thermal via and the first electrical via have different materials and the same height.
    Type: Application
    Filed: October 22, 2018
    Publication date: May 30, 2019
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jhih-Yang YAN, Fang-Liang LU, Chee-Wee LIU
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190165141
    Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.
    Type: Application
    Filed: October 2, 2018
    Publication date: May 30, 2019
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Fang-Liang LU, Pin-Shiang CHEN, Chee-Wee LIU