Patents by Inventor Cheehoe Teh

Cheehoe Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for performing design rule check on mask pattern data for an integrated circuit
    Patent number: 7552408
    Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: June 23, 2009
    Assignee: United Microelectronics Corporation
    Inventors: Cheehoe Teh, Nimcho Lam, Mau Truong
  • System & method for performing design rule check
    Publication number: 20050086619
    Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.
    Type: Application
    Filed: November 5, 2004
    Publication date: April 21, 2005
    Inventors: Cheehoe Teh, Nimcho Lam, Mau Truong
  • System and method for performing design rule check
    Patent number: 6816997
    Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: November 9, 2004
    Inventors: Cheehoe Teh, Nimcho Lam, Mau Truong
  • System & method for performing design rule check
    Publication number: 20020138813
    Abstract: An improved system and method is disclosed for performing a design rule check on a proposed integrated circuit (IC) layout, and for creating customized design rule check command files. The individual layers of the IC (a system on chip—SOC) are separated into different regions having different kinds of features (i.e., memory or logic). Each different type of region is then analyzed in accordance with the customized design rule command file so that so-called “false errors” are eliminated. The invention thus improves, among other things, a development time for getting a design implemented in silicon.
    Type: Application
    Filed: March 20, 2002
    Publication date: September 26, 2002
    Inventors: Cheehoe Teh, Nimcho Lam, Mau Truong