Patents by Inventor Chen-Chung Lai

Chen-Chung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437361
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen Lai, Lin Chung-Yi, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 10777480
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Publication number: 20200111719
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 10515866
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Publication number: 20190115273
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 10204843
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 10157810
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 10014251
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Publication number: 20180076109
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 15, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Publication number: 20180012818
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9818666
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 9773716
    Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9761486
    Abstract: A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first layer, a passivation layer over the first layer, a second layer over the passivation layer, and a third layer over the second layer. The method also comprises forming a patterned opening having multiple depths by removing portions of the first layer, the passivation layer, the second layer, and the third layer by way of one or more removal processes that remove portions of the first layer, the passivation layer, the second layer, and the third layer in accordance with one or more patterned photoresist depositions. The method further comprises depositing a material into the patterned opening, and leveling the material deposited into the patterned opening.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gwo-Chyuan Kuo, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20170033030
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9472508
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20160247741
    Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9412866
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gwo-Chyuan Kuoh, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien, Yen-Ming Peng
  • Patent number: 9406559
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Han-Wei Yang, Chen-Chung Lai, Song-Bor Lee
  • Publication number: 20160190064
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Application
    Filed: March 5, 2016
    Publication date: June 30, 2016
    Inventors: Chen-Chung LAI, Kang-Min KUO, Yen-Ming PENG, Gwo-Chyuan KUOH, Han-Wei YANG, Yi-Ruei LIN, Chin-Chia CHANG, Ying-Chieh LIAO, Che-Chia HSU, Bor-Zen TIEN
  • Patent number: 9349688
    Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien