Patents by Inventor Chen-Hsien LIU

Chen-Hsien LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359552
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
  • Patent number: 11430768
    Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 30, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzu-Hsuan Wang, Chen-Hsien Liu
  • Patent number: 11430799
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Publication number: 20220269130
    Abstract: A backlight module including a substrate, light-emitting elements, an optical element, first microstructures, and second microstructures is provided. The light-emitting elements are disposed on the substrate. The light-emitting elements are located between the optical element and the substrate. The first microstructures are located between the optical element and the light-emitting elements and respectively shield the light-emitting elements. The optical element is located between the second microstructures and the first microstructures. An area of each of the first microstructures is greater than an area of each of the second microstructures. Moreover, a display apparatus including the backlight module is also provided.
    Type: Application
    Filed: January 26, 2022
    Publication date: August 25, 2022
    Applicant: Coretronic Corporation
    Inventors: Cheng-Hsien Chou, Chen-Hung Lin, Yu-Yu Liu
  • Patent number: 11397998
    Abstract: A method is proposed to assist a user of an electric vehicle in reserving a rechargeable battery with a charging station. A reservation assistant unit that is related to the electric vehicle computes an estimated travelling distance from a current location corresponding to the electric vehicle to a destination, and computes a remaining distance based on residual electric energy of a rechargeable battery currently used by the electric vehicle. When the estimated travelling distance is greater than the remaining distance, the reservation assistant unit provides charging station information that indicates the closest charging station that has a rechargeable battery available.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 26, 2022
    Assignee: KWANG YANG MOTOR CO., LTD.
    Inventors: Chen-Sheng Lin, Sen-Hsien Chang, Jen-Chiun Lin, Po-Yu Chuang, Yuh-Rey Chen, Te-Chuan Liu
  • Publication number: 20220189923
    Abstract: A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 16, 2022
    Inventors: Tzu-Hsuan WANG, Chen-Hsien LIU