Patents by Inventor Chen-Hsiung Yang
Chen-Hsiung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230192476Abstract: A MEMS device includes a first multi-layer structure, a second multi-layer structure over the first multi-layer structure, a first semiconductor layer between the first and second multilayer structures, a first air gap separating the first multi-layer structure and the first semiconductor layer, a second air gap separating the first semiconductor layer and the second multi-layer structure, a plurality of semiconductor pillars, and a plurality of second semiconductor pillars. The first semiconductor pillars are exposed to the first air gap, and coupled to the first semiconductor layer and the first multi-layer structure. The second semiconductor pillars are exposed to the second air gap, and coupled to the first semiconductor layer and the second multi-layer structure.Type: ApplicationFiled: February 12, 2023Publication date: June 22, 2023Inventors: CHEN HSIUNG YANG, CHUN-WEN CHENG, CHIA-HUA CHU, EN-CHAN CHEN
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Patent number: 11577954Abstract: A method for forming a MEMS device includes following operations. A first semiconductor layer is formed over a substrate. A plurality of first pillars are formed over the first layer. A second layer is formed over the first pillars and the first layer. A plurality of second pillars are formed over the second layer. A third layer is formed over the second pillars and the second layer.Type: GrantFiled: December 7, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
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Patent number: 11206493Abstract: A micro electro mechanical system (MEMS) microphone includes a first membrane, a second membrane, a third membrane disposed between the first membrane and the second membrane, a first cavity disposed between the first membrane and the third membrane and surrounded by a first wall, a second cavity disposed between the second membrane and the third membrane and surrounded by a second wall, and one or more first supports disposed in the first cavity and connecting the first membrane and the third membrane.Type: GrantFiled: October 29, 2018Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
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Patent number: 11186481Abstract: A sensor device includes a microelectromechanical system (MEMS) force sensor, and a capacitive acceleration sensor. In the method of manufacturing the sensor device, a sensor portion of the MEMS force sensor is prepared over a front surface of a first substrate. The sensor portion includes a piezo-resistive element and a front electrode. A bottom electrode and a first electrode are formed on a back surface of the first substrate. A second substrate having an electrode pad and a second electrode to the bottom of the first substrate are attached such that the bottom electrode is connected to the electrode pad and the first electrode faces the second electrode with a space therebetween.Type: GrantFiled: November 2, 2018Date of Patent: November 30, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Jiou-Kang Lee
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Publication number: 20210087052Abstract: A method for forming a MEMS device includes following operations. A first semiconductor layer is formed over a substrate. A plurality of first pillars are formed over the first layer. A second layer is formed over the first pillars and the first layer. A plurality of second pillars are formed over the second layer. A third layer is formed over the second pillars and the second layer.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventors: CHEN HSIUNG YANG, CHUN-WEN CHENG, CHIA-HUA CHU, EN-CHAN CHEN
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Patent number: 10865099Abstract: A MEMS device includes a first layer and a second layer including a same material, a third layer disposed between the first layer and the second layer, a first air gap separating the first layer and the third layer, a second air gap separating the second layer and the third layer, a plurality of first pillars exposed to the first air gap and arranged in contact with the first layer and the third layer, a plurality of second pillars exposed to the second air gap and arranged in contact with the second layer and the third layer.Type: GrantFiled: August 29, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
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Publication number: 20200071157Abstract: A MEMS device includes a first layer and a second layer including a same material, a third layer disposed between the first layer and the second layer, a first air gap separating the first layer and the third layer, a second air gap separating the second layer and the third layer, a plurality of first pillars exposed to the first air gap and arranged in contact with the first layer and the third layer, a plurality of second pillars exposed to the second air gap and arranged in contact with the second layer and the third layer.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Inventors: CHEN HSIUNG YANG, CHUN-WEN CHENG, CHIA-HUA CHU, EN-CHAN CHEN
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Publication number: 20190306633Abstract: A micro electro mechanical system (MEMS) microphone includes a first membrane, a second membrane, a third membrane disposed between the first membrane and the second membrane, a first cavity disposed between the first membrane and the third membrane and surrounded by a first wall, a second cavity disposed between the second membrane and the third membrane and surrounded by a second wall, and one or more first supports disposed in the first cavity and connecting the first membrane and the third membrane.Type: ApplicationFiled: October 29, 2018Publication date: October 3, 2019Inventors: Chen Hsiung YANG, Chun-Wen CHENG, Chia-Hua CHU, En-Chan CHEN
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Publication number: 20190162753Abstract: A sensor device includes a microelectromechanical system (MEMS) force sensor, and a capacitive acceleration sensor. In the method of manufacturing the sensor device, a sensor portion of the MEMS force sensor is prepared over a front surface of a first substrate. The sensor portion includes a piezo-resistive element and a front electrode. A bottom electrode and a first electrode are formed on a back surface of the first substrate. A second substrate having an electrode pad and a second electrode to the bottom of the first substrate are attached such that the bottom electrode is connected to the electrode pad and the first electrode faces the second electrode with a space therebetween.Type: ApplicationFiled: November 2, 2018Publication date: May 30, 2019Inventors: Chen Hsiung YANG, Chun-Wen CHENG, Jiou-Kang LEE
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Patent number: 10087071Abstract: A semiconductor structure includes a first substrate, a second substrate disposed over the first substrate, and including a first surface, a second surface opposite to the first surface, a via portion extending between the first surface and the second surface, a first through hole and a second through hole, and a device disposed over the second surface, and including a dielectric layer, a backplate at least partially exposed from the dielectric layer and a membrane at least partially exposed from the dielectric layer and disposed between the backplate and the first substrate, wherein the via portion is disposed within the second through hole, and the dielectric layer is bonded with the second substrate, and the device is electrically connected to the first substrate through the via portion.Type: GrantFiled: October 25, 2016Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzu-Heng Wu, Chia-Hua Chu, Yi-Heng Tsai, Cheng San Chou, Chen Hsiung Yang
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Publication number: 20180111824Abstract: A semiconductor structure includes a first substrate, a second substrate disposed over the first substrate, and including a first surface, a second surface opposite to the first surface, a via portion extending between the first surface and the second surface, a first through hole and a second through hole, and a device disposed over the second surface, and including a dielectric layer, a backplate at least partially exposed from the dielectric layer and a membrane at least partially exposed from the dielectric layer and disposed between the backplate and the first substrate, wherein the via portion is disposed within the second through hole, and the dielectric layer is bonded with the second substrate, and the device is electrically connected to the first substrate through the via portion.Type: ApplicationFiled: October 25, 2016Publication date: April 26, 2018Inventors: TZU-HENG WU, CHIA-HUA CHU, YI-HENG TSAI, CHENG SAN CHOU, CHEN HSIUNG YANG
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Patent number: 9550667Abstract: A semiconductor structure includes a first substrate, a second substrate, a first sensing structure over the first substrate, and between the first substrate and the second substrate, a via extending through the second substrate, and a second sensing structure over the second substrate, and including an interconnect structure electrically connected with the via, and a sensing material at least partially covering the interconnect structure.Type: GrantFiled: September 8, 2015Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTRUING COMPANY LTD.Inventors: Cheng San Chou, Chin-Min Lin, Chen Hsiung Yang
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Patent number: 7582511Abstract: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.Type: GrantFiled: May 17, 2006Date of Patent: September 1, 2009Assignee: Touch Micro-System Technology Inc.Inventor: Chen Hsiung Yang
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Patent number: 7566574Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.Type: GrantFiled: September 6, 2007Date of Patent: July 28, 2009Assignee: Touch Micro-System Technology Inc.Inventor: Chen-Hsiung Yang
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Patent number: 7531457Abstract: A method of fabricating a suspended structure. First, a substrate including a photoresist layer hardened by heat is provided. Subsequently, the hardened photoresist layer is etched so as to turn the photoresist layer into a predetermined edge profile. Thereafter, a structure layer is formed on parts of the substrate and parts of the photoresist layer. Next, a dry etching process is performed so as to remove the photoresist layer, and to turn the structure layer into a suspended structure.Type: GrantFiled: November 21, 2006Date of Patent: May 12, 2009Assignee: Touch Micro-System Technology Inc.Inventors: Yu-Fu Kang, Chen-Hsiung Yang
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Patent number: 7505118Abstract: A wafer carrier for carrying a wafer includes a transparent base and a conducting layer. The transparent base has dimensions similar to that of the wafer, and bonds the wafer with a bonding layer. The conducting layer is transparent, and can be attracted by an electrostatic chuck so that the electrostatic chuck can deliver the wafer.Type: GrantFiled: October 12, 2004Date of Patent: March 17, 2009Assignee: Touch Micro-System Technology Inc.Inventor: Chen-Hsiung Yang
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Patent number: 7465601Abstract: A method of forming a suspended structure is disclosed. Initially, a substrate is provided. A patterned first sacrificial layer and a patterned second sacrificial layer are formed on a front surface of the substrate. The second sacrificial layer has an opening exposing a part of the substrate and a part of the first sacrificial layer. A structural layer is formed covering the abovementioned sacrificial layers. Thereafter, a lift-off process is performed to remove the second sacrificial layer and define the pattern of the structural layer. A first etching process is performed on a back surface of the substrate utilizing the first sacrificial layer as an etching barrier and a through hole is formed under the first sacrificial layer. A second etching layer is performed to remove the first sacrificial layer and a suspended structure is thereby formed.Type: GrantFiled: April 18, 2007Date of Patent: December 16, 2008Assignee: Touch Micro-System Technology Inc.Inventors: Yu-Fu Kang, Chen-Hsiung Yang
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Patent number: 7410835Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.Type: GrantFiled: December 6, 2005Date of Patent: August 12, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jui-Hsiang Hung, Chin-Teng Hsu, Chen-Hsiung Yang, Chih-Jen Yang
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Publication number: 20080138923Abstract: A method of forming a suspended structure is disclosed. Initially, a substrate is provided. A patterned first sacrificial layer and a patterned second sacrificial layer are formed on a front surface of the substrate. The second sacrificial layer has an opening exposing a part of the substrate and a part of the first sacrificial layer. A structural layer is formed covering the abovementioned sacrificial layers. Thereafter, a lift-off process is performed to remove the second sacrificial layer and define the pattern of the structural layer. A first etching process is performed on a back surface of the substrate utilizing the first sacrificial layer as an etching barrier and a through hole is formed under the first sacrificial layer. A second etching layer is performed to remove the first sacrificial layer and a suspended structure is thereby formed.Type: ApplicationFiled: April 18, 2007Publication date: June 12, 2008Inventors: Yu-Fu Kang, Chen-Hsiung Yang
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Publication number: 20070298582Abstract: A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled into the front scribe lines. Subsequently, the structural pattern is bonded to a carrier wafer with a bonding layer, and a plurality of back scribe lines are defined on the back surface of the wafer. Finally, the filling layer filled in the front scribe lines is removed.Type: ApplicationFiled: September 6, 2007Publication date: December 27, 2007Inventor: Chen-Hsiung Yang