Patents by Inventor Chen-Che Huang
Chen-Che Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11916018Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.Type: GrantFiled: March 4, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Yi Weng, Shih-Che Huang, Ching-Li Yang, Chih-Sheng Chang
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Publication number: 20170272919Abstract: A method for providing push-to-talk communication service is provided. The method is used in a broadcast server and includes: receiving an invitation message from a calling device; broadcasting a plurality of push-to-talk invitation messages to a plurality of called devices identified in a group list associated with the calling device; and receiving a plurality of push-to-talk acknowledgment messages from the called devices to establish a first voice transmission path between the broadcast server and the called devices.Type: ApplicationFiled: June 23, 2016Publication date: September 21, 2017Inventors: Yu-Hsing LIN, Chen-Che HUANG, Chung-Kuo HUANG, Yu-Chuan CHANG, Chun-Hsiung FANG
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Patent number: 9736429Abstract: A cloud video system is provided. The cloud video system includes: a cloud server and a plurality of clients. The clients are connected to the cloud server via a network, and each client has an individual role. When the first of the clients has established a video session call with other clients, the cloud server determines whether to record the video session call according to the individual role of each client in the video session call.Type: GrantFiled: June 9, 2016Date of Patent: August 15, 2017Assignee: QUANTA COMPUTER INC.Inventors: Chen-Che Huang, Yu-Hsing Lin, Chin-Yuan Ting, Chun-Hsiung Fang, Hung-Bin Lin, Shih-Ming Chen
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Publication number: 20160259891Abstract: A telehealth care system is configured to provide a first service, in which the first service includes a first operation and a second operation. The telehealth care system includes a first host terminal, first electronic devices, and a central data center. The first electronic devices are configured to correspond to the first host terminal. The central data center is connected to the first host terminal and the first electronic devices. The first electronic devices are configured to perform the first operation via the central data center, and to perform the second operation via the first host terminal. The data processed by the first operation has a first data attribute, the data processed by the second operation has a second data attribute that is different from the first data attribute.Type: ApplicationFiled: June 9, 2015Publication date: September 8, 2016Applicant: QUANTA COMPUTER INC.Inventors: Rong-Quen CHEN, Chun-Hsiung FANG, Kai-Ju CHENG, Chen-Che HUANG, Chia-Han WU, Chia-Hua HU, Li-An CHUANG, Hsin-Lun HSIEH
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Patent number: 8658335Abstract: A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.Type: GrantFiled: October 16, 2012Date of Patent: February 25, 2014Assignee: SanDisk Technologies Inc.Inventors: Chen-Che Huang, Chun-Ming Wang, Masaaki Higashitani
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Patent number: 8325529Abstract: Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad.Type: GrantFiled: June 10, 2010Date of Patent: December 4, 2012Assignee: SanDisk Technologies Inc.Inventors: Chen-Che Huang, Chun-Ming Wang, Masaaki Higashitani
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Patent number: 8313992Abstract: A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.Type: GrantFiled: October 4, 2010Date of Patent: November 20, 2012Assignee: SanDisk Technologies Inc.Inventors: Chen-Che Huang, Chun-Ming Wang, Masaaki Higashitani
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Patent number: 8221943Abstract: A photomask for exposure of a semiconductor wafer using dipole illumination and method of manufacturing the same is disclosed. A method of forming a pattern on a semiconductor using the photomask is also disclosed. The photomask may have an array of islands that are used for printing lines using dipole illumination. The photomask may have sub-resolution assist features (SRAF) to assist in printing the lines. The SRAF may include an array of holes.Type: GrantFiled: March 22, 2010Date of Patent: July 17, 2012Assignee: SanDisk Technologies Inc.Inventors: Chun-Ming Wang, Chen-Che Huang, Masaaki Higashitani
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Publication number: 20120083124Abstract: A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: SanDisk CorporationInventors: Chen-Che Huang, Chun-Ming Wang, Masaaki Higashitani
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Publication number: 20110229805Abstract: A photomask for exposure of a semiconductor wafer using dipole illumination and method of manufacturing the same is disclosed. A method of forming a pattern on a semiconductor using the photomask is also disclosed. The photomask may have an array of islands that are used for printing lines using dipole illumination. The photomask may have sub-resolution assist features (SRAF) to assist in printing the lines. The SRAF may include an array of holes.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Inventors: Chun-Ming Wang, Chen-Che Huang, Masaaki Higashitani
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Publication number: 20110026327Abstract: Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad.Type: ApplicationFiled: June 10, 2010Publication date: February 3, 2011Inventors: Chen-Che Huang, Chun-Ming Wang, Masaaki Higashitani
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Patent number: 7871909Abstract: Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ? the width of lines in the first pattern.Type: GrantFiled: January 19, 2010Date of Patent: January 18, 2011Assignee: SanDisk 3D LLCInventors: Chun-Ming Wang, Chen-Che Huang, Masaaki Higashitani, George Matamis
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Patent number: D930699Type: GrantFiled: January 7, 2019Date of Patent: September 14, 2021Assignee: Kentai Machinery Co., Ltd.Inventor: Chen-Che Huang